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cywb022xx family west bridge ? : astoria? usb and mass storage peripheral controller cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 001-13805 rev. *m revised july 6, 2012 west bridge ? : astoria? usb and mass storage peripheral controller features multimedia device support ? up to two sd, sdio, mmc, mmc+, and ce-ata devices supports microsoft ? media transfer protocol (mtp) with optimized data throughput simultaneous link to independent multimedia (slim ? ) architecture, enabling simultaneous and independent data paths between the processor and usb, and between the usb and mass storage high-speed usb at 480 mbps ? usb 2.0 compliant ? integrated usb switch ? integrated usb 2.0 transceiver, smart serial interface engine ? 16 programmable endpoints gpif (general programmable interface) ? allows direct connection to most parallel interface ? programmable waveform descriptors and configuration registers to define waveforms ? supports multiple ready (rdy) inputs and control (ctl) outputs flexible processor interface that supports: ? multiplexing and nonmultiplexing address and data interface ? sram interface ? pseudo cellular random access memory (cram) interface (antioch interface) ? pseudo nand flash interface ? spi (slave mo de) interface ? direct memory access (dma) slave support flexboot ? processor can boot from the processor interface port ultra low power, 1.8-v core operation low power modes small footprint: ? 3.91 3.91 0.55 mm 81-ball wlcsp (sp and lite sp) ? 6 6 1.0 mm 100-ball vfbga ? 10 10 1.20 mm 121-ball fbga supports i 2 c boot and processor boot selectable clock input frequencies ? 19.2 mhz, 24 mhz, 26 mhz, and 48 mhz applications cellular phones portable media players personal digital assistants portable navigation devices digital cameras pos terminals portable video recorders data cards and wireless dongles west bridge tm astoria tm flexible processor interface control registers uc high-speed usb 2.0 xcvr u p s slim tm access control cypress n-xpress tm engine configurable storage interface sd/sdio/ mmc+/ ce- ata block logic block diagram
cywb022xx family document number: 001-13805 rev. *m page 2 of 78 contents functional overview ........................................................ 3 turbo-mtp support ..... .............. .............. ........... ......... 3 slim architecture ........................................................ 3 8051 microprocessor ... .............. .............. ........... ......... 3 configuration and status registers ............................. 3 processor interface (p-port) ........................................ 3 flexboot ...................................................................... 3 usb interface (u-port) ................................................ 3 mass storage support (s-port) ............ .............. ......... 4 clocking ....................................................................... 5 power domains ........................................................... 6 power modes .............................................................. 7 packages and interface options .............. .............. ......... 8 pin assignments .............................................................. 9 absolute maximum ratings .......................................... 32 operating conditions ..................................................... 32 dc characteristics ......................................................... 33 ac timing parameters ......... .......................................... 35 p port interface ......................................................... 35 s port interface ac timing parameters .................... 68 reset and standby timing parameters .................... 69 ordering information ...................................................... 71 ordering code definitions ..... .................................... 71 package diagram ............................................................ 72 acronyms ........................................................................ 75 document conventions ................................................. 75 units of measure ....................................................... 75 document history page ................................................. 76 sales, solutions, and legal information ...................... 78 worldwide sales and design s upport ......... .............. 78 products .................................................................... 78 psoc solutions ......................................................... 78
cywb022xx family document number: 001-13805 rev. *m page 3 of 78 functional overview turbo-mtp support turbo-mtp is an implementation of microsoft?s mtp enabled by west bridge. in the current ge neration of mtp-enabled mobile phones, all protocol packets needs to be handled by the main processor. west bridge turbo- mtp switches these packet types and sends only control packets to the processor, while data payloads are written directly to mass storage, thereby bringing the high performance of west bridge to mtp. for more information refer to the application note optimizing performance using west bridge ? controllers with turbo-mtp . slim architecture the slim architecture enables thr ee different interfaces (p-port, s-port, and u-port) to connect to one another independently. with this architecture, connecting a device using astoria to a pc through usb does not disturb any of the functions of the device. the device can still access mass storage at the same time as the pc synchronizes with the main processor. the slim architecture enables new usage models in which a pc can access a mass storage device independent of the main processor or enumerate access to both the mass storage and the main processor at the same time. in a handset, this typically enables using the phone as a thumb drive, downloading media files to the phone while still having full functionality available on the phone, or using the same phone as a modem to connect the pc to the web. 8051 microprocessor the 8051 microprocessor embedded in astoria does basic transaction management for all th e transactions between p-port, s-port, and u-port. the 8051 does not reside in the data path; it manages the path. the data path is optimized for performance. the 8051 executes firmware that supports sd, sdio, mmc+, and ce-ata devices at the s-port. configuration and status registers the west bridge astoria device includes configuration and status registers that are accessi ble as memory mapped registers through the processor interface. the configuration registers allow the system to specify certain astoria behaviors. for example, it is able to mask certain status registers from raising an interrupt. the status registers convey various status such as the addresses of buffers for read operations. processor interface (p-port) communication with the external processor is realized through a dedicated processor interface. th is interface is configured to support different interface standards. this interface supports multiplexing and nonmultiplexing address or data bus in both synchronous and asynchronous pseudo cram-mapped, and nonmultiplexing address or data asynchronous sram-mapped memory accesses. the interface also can be configured to a pseudo nand interface to su pport the processor?s nand interface. in addition, this inte rface can be configured to support spi slave. asynchronous accesses can reach a bandwidth of up to 66.7 mbps. synchronous accesses can be performed at 33 mhz across 16 bits for up to 66.7 mbps bandwidth. the p-port of the wlcsp package only supports pnand and spi interface. the memory address is decoded to access any of the multiple endpoint buffers inside astoria. these endpoints serve as buffers for data between each pair of ports, for example, between the processor port and the usb port. the processor writes and reads into these buffers through the memory interface. access to these buffers is controlled by either using a dma protocol or using an interrupt to the main processor. these two modes are configurable by the ex ternal processor. the 81-ball wlcsp package only supports interrupt. as a dma slave, astoria gener ates a dma request signal to signify to the main processor that a specific buffer is ready to be read from or written to. the external processor monitors this signal and polls astoria for the specific buffers ready for read or write. it then performs the appr opriate read or write operations on the buffer through the processor interface. this way, the external processor only deals wi th the buffers to access a multitude of storage devices connected to astoria. in the interrupt mode, astori a communicates important buffer status changes to the external processor using an interrupt signal. the external processor then polls astoria for the specific buffers ready for read or write and it performs the appropriate read or write operations through the processor interface. flexboot flexboot is an optional feature that astoria emulates a nand flash device. in this optional feat ure, the p-port is configured as pseudo nand interface. the processor can download its boot image through the p-port. when p-port is configured to pseudo nand interface, it supports two operation modes: logic nand access (lna) mode non-logic nand access (non-lna) mode lna refers to the mode of operation where astoria emulates a nand flash device. this mode is designed for systems that require booting of the system processor from a nand flash device. in this type of applic ation, the system processor can communicate to astoria using common nand commands to boot from a nand flash connected to astoria?s s-port. in this mode of operation, astoria mimics a real nand device and allows the system processor to us e its internal boot-rom to boot from astoria, as it boots from a nand flash. in the non-lna mode of operation, the system processor interfaces with astoria using standard nand interface, but does not use standard nand commands. in this mode, astoria responds to a subset of nand commands. the system processor uses a set of apis provided by cypress to communicate through its nand cont roller to astoria. for details, refer to the application note ?interfacing to west bridge? astoria?s? pseudo-nand processor port ?. usb interface (u-port) in accordance with the usb 2.0 specification, astoria can operate in both full speed and high speed usb modes. the usb interface consists of the usb transceiver and can be accessed by both the p-port and the s-port.
cywb022xx family document number: 001-13805 rev. *m page 4 of 78 the astoria usb interface supports programmable control/bulk/interrupt/isochronous endpoints. astoria also has an integrated usb switch (see figure 1 ) that allows interfacing to an external full speed usb phy. figure 1. u-port with switch and control block mass storage support (s-port) the s-port is configurable in five different interface modes: simultaneously supporting an sd/sdio/mmc+/ce-ata port and an gpif supporting two sd/sdio/mmc+/ce-ata ports supporting sd/sdio/mmc+/ce-ata port and gpio supporting gpif and gpio supporting gpio these configurations are controlled by the 8051 firmware. s-port configuration modes the s port is configurable in six different interface modes: gpif and sd/sdio/mmc/ce-ata interface mode dual sd/sdio/mmc/ce-ata interface mode sd/sdio/mmc/ce-ata and gpio interlace mode gpif and gpio interface mode gpio interface mode gpif and sd/sdio/mmc/ce-ata interface mode this mode configures the s-port into gpif and sd/sdio/mmc/mmc+/ce-ata ports as shown in figure 2 . the sd/sdio/mmc/mmc+/ce-ata port supports eit her sd, sdio, mmc, mmc+, or ce-ata device. figure 2. gpif and sd/sdio/mmc/ce-ata interface mode dual sd/sdio/mmc/ce-ata interface mode the dual sd/sdio/mmc/mmc +/ce-ata interface mode configures the s-port for up to two sd/sdio/mmc/mmc+/ce-ata port as shown in figure 3 . each sd/sdio/mmc/mmc+/ce-ata port is independent and supports different sd, sdio, mmc, mmc+, or ce-ata devices. figure 3. dual sd/sdi o/mmc/ce-ata interface mode sd/sdio/mmc/ce-ata and gpio interface the sd/sdio/mmc/mmc+/ce-ata and gpio interface mode configures the s-port to support sd/sdio/mmc/mmc+/ce-ata device and gpios as shown in figure 4 . each gpio is configured as either input or output independently. the processor accesses those gpio through the p-port driver?s api. figure 4. sd/sdio/mmc/ce-ata and gpio interface mode d+ d- usb 2.0 xcvr usb port (u port) usb switch and control block swd+ swd- usballo uvalid sd sdio mmc mmc+ ce-ata or or or or sd_d[7:0] sd sdio mmc mmc+ ce-ata or or or or sd2_d[7:0] astoria s port p port u port sd sdio mmc mmc+ ce-ata or or or or sd_d[7:0] pb[7:0] gpio astoria s port p port u port
cywb022xx family document number: 001-13805 rev. *m page 5 of 78 gpif and gpio interface the gpif and gpio interface mode configure the s-port to support gpif and gpio as shown in figure 5 . each gpio is configured as either input or output independently. the processor accesses those gpio through the p-port driver?s api. figure 5. gpif and gpio interface mode gpio interface mode the gpio interface mode configur es the s-port to all gpio as shown in figure 6 . each gpio is configured as either input or output independently. the processor accesses those gpio through the p-port driver?s api. figure 6. gpio interface mode sd/sdio/mmc+/ce-ata port (s-port) when astoria is configured with firmware to support sd, sdio, mmc+, and ce-ata, this interface supports: the multimedia card system specification, mmca technical committee, version 4.1 sd memory card specification ? part 1, physical layer specification, sd group, version 1.10, october 15, 2004 sd memory card specification ? part 1, physical layer specification, sd group, version 2.0, may 9, 2006 sd specifications ? part e1 sd io specification, version 1.10, august 18, 2004 ce-ata specification ? ce-ata digital protocol, ce-ata committee, version 1.1, september, 2005 west bridge astoria provides support for 1-bit and 4-bit sd; sdio cards; 1-bit, 4-bit, and 8-bit mmc; mmc+ cards; and ce-ata drive. for the sd, sdio, mmc/mmc plus, and ce-ata, this block supports one card for one physical bus interface. astoria supports sd commands including the multisector program command that are handled by the api. gpio port (s-port) the gpio in s-port is configur able as either input or output direction independently. the processor accesses the gpio through the p-port driver?s api. clocking astoria allows connection of a crystal between the xtalin and xtalout pins or an external clock at the xtalin pin. the 81-ball wlcsp package only supports the external clock. the power supply level at the crystal supply xvddq determines whether a crystal or a clock is provided. if xvddq is detected to be 1.8 v, astoria assumes that a clock input is provided. for a crystal to be connected, xvddq must be 3.3 v. note clock inputs at 3.3 v level are not supported. astoria?s 100-ball vfbga package supports external crystal and clock inputs at 19.2, 24, and 26 mhz frequencies. at 48 mhz, only clock inputs are supported. the 81-ball spwlcsp only supports 19.2 and 26 mhz external clock input. the 81-ball lite sp wlcsp only supports 26 mhz external clock or crystal input. the crystal or clock frequency selection is shown in table 1 on page 6 , table 2 on page 6 , and table 3 on page 6 . the xtalin frequency is independent of the clock and data rate of the 8051 microprocessor or any of the device interfaces (including p-port and s-port). the internal pll applies the proper clock multiply option depending on the input frequency. for applications that use an external clock source to drive xtalin, the xtalout pin must be left floating. the external clock source must also stop high or low and not toggle, to achieve the lowest possible current consumption. the requirements for an external clock source are shown in table 4 on page 6 . astoria has an on-chip oscillator circuit that uses an external 19.2, 24, and 26 mhz (150 ppm) crystal with the following characteristics: parallel resonant fundamental mode 1 mw drive level 12 pf (5% tolerance) load capacitors 150 ppm gpio astoria s port p port u port
cywb022xx family document number: 001-13805 rev. *m page 6 of 78 figure 7. crystal configuration power domains astoria has multiple power domains that serve different purposes within the chip. vddq refers to a group of four independent supply domains for the digital i/os. the nominal voltage level on these supplies are 1.8 v, 2.5 v, or 3.3 v. the three separate i/o power domains are: ? pvddq ? p-port processor interface i/o ? snvddq ? s-port gpif interface i/o ? ssvddq ? s-port sd interface i/o ? gvddq ? other miscellaneous i/o uvddq is the 3.3-v nominal supply for the usb i/o and some analog circuits. it also supplies power to the usb transceiver vdd33 supply is required fo r the power sequence control circuits. for more details, see pin assignments on page 9 . vdd is the supply voltage for the logic core. the nominal supply voltage level is 1.8 v. this supplies the core logic circuits. the same supply must also be used for avddq avddq is the 1.8 v supply for pll and usb serializer analog components. the same supply must also be used for vdd. the maximum permitted noise on avddq is 20 mv p-p xvddq is the clock i/o supply; 3.3 v for xtal or 1.8 v for an external clock noise guideline for all supplies except avddq is a maximum of 100 mv p-p. all i/o supplies of astoria must be on when a system is active even if astoria is not in use. the core vdd can also be deactivated at any time to preserve power if there is a minimum impedance of 1 k ? between the vdd pin and ground. all i/os tristate when the core is disabled. astoria xtalin xtalout pll 12pf 12pf xtal * 12 pf capacitor values assumes a trace capacitance of 3 pf per side on a four layer fr4 pca table 1. 100-ball fvbga clock selection xtalslc[1] xtalslc[0] freq crystal/clock 0 0 19.2 mhz crystal/clock 0 1 24 mhz crystal/clock 1 0 48 mhz clock 1 1 26 mhz crystal/clock table 2. 81-ball sp wlcsp clock selection xtalslc freq crystal/clock 0 19.2 mhz clock 1 26 mhz clock table 3. 81-ball lite sp wlcsp clock supports 26 mhz xtalslc freq crystal/clock na 26 mhz clock or crystal table 4. external clock requirements parameter description specification unit min max vn (avddq) supply voltage noise at frequencies < 50 mhz ? 20 mv p-p pn_100 input phase noise at 100 hz ? ?75 dbc/hz pn_1k input phase noise at 1 khz offset ? ?104 dbc/hz pn_10k input phase noise at 10 khz offset ? ?120 dbc/hz pn_100k input phase noise at 100 khz offset ? ?128 dbc/hz pn_1m input phase noise at 1 mhz offset ? ?130 dbc/hz duty cycle 30 70 % maximum frequency deviation ? 150 ppm overshoot ?3% undershoot ??3%
cywb022xx family document number: 001-13805 rev. *m page 7 of 78 figure 8. astoria power supply domains power supply sequence the power supplies are independently sequenced without damaging the part. all power supplies must be up and stable before the device operates. if the supplies are not stable, the remaining domains are in low power (standby) state. power modes in addition to the normal operating mode, astoria contains several low power states when normal operation is not required. normal mode normal mode is the mode in whic h astoria is fully functional. in this mode, data transfer functions described in this document are performed. suspend mode this mode is entered internally by 8051 (the external processor only initiates entry into this mode through mailbox commands). this mode is exited by the d+ bus going low, gpio[0] going to a pre-determined state or by asserting ce# low. in astoria?s suspend mode: the clocks are shut off all i/os maintain their previous state core power supply must be retained the states of the configuration registers, endpoint buffers, and the program ram are maintained. all transactions must be complete before astoria enters suspend mode (state of outstanding transactions are not preserved) the firmware resumes its operation from where it was suspended because the program counter is not reset only inputs that are sensed are reset#, gpio[0]/sd_cd, gpio[1]/sd2_cd, sd_d3, sd2_d3, d+, and ce#. the last three are wake up sources (each can be individually enabled or disabled) hard reset can be performed by asserting the reset# input, and astoria is initialized standby mode standby mode is a low-power state. this is the lowest power mode of astoria while still maintaining external supply levels. this mode is entered through the deassertion of the wakeup input pin or through internal register settings. to leave this mode, assert the wakeup, ce#, and reset#; change state of gpio[0]/sd_cd, gpio[1]/sd 2_cd, sd_d3, and sd2_d3. in this mode all configuration register settings and program ram contents are preserved. however, data in the buffers or other parts of the data path, if any, is not guaranteed in values. therefore, the external processo r must ensure that the required data is read before placing astoria in the standby mode. in the standby mode: the program counter is reset on waking up from standby mode all outputs are tristated and i/o is placed in input only configuration. values of i/os in standby mode are listed in the pin assignments table core power supply must be retained hard reset can be performed by asserting the reset# input, and astoria is initialized pll is disabled usb switches the swd+/swd? to d+/d? core power down mode the core power supply v dd is powered down in this state. because avddq is tied to the same supply as v dd , it is also powered down. the endpoint buffers, configuration registers, and program ram do not mainta in state. all vddq power supplies (except avddq) must be on and not power down in this mode. vdd33 must also remain on. it has an option that the uvddq can be powered down or stay on while v dd is powered down when swd+/swd? are not connected. the uvddq cannot be powered down when swd+/swd? is connected, or v dd is active. when uvddq is powered down, d+/d? cannot be driven by an external device. in the wlcsp package, avddq is internally tied to xvddq. due to this, the clock input at xtalin must be brought to a steady low level prior to entry into core power down mode. in the wlcsp package, vdd33 is tied to uvddq internally. uvddq must be on during the core power down mode the core power down mode has two power down options: core only power down ? vdd power down core and usb power down ? vdd and uvddq are both powered down. in this option, swd+/swd? are not connected and cannot be driven by an external device in these power down options, the endpoint buffers, configuration registers, or the program ram do not maintain state. it is necessary to reload the firmware on exiting from this mode. all vddq power supplies must be on and not powered down in this mode. in the 82-ball wlcsp package, in the core power down mode, the usb switches the swd+/swd? to d+/d?. usb-io d-core i/o uvddq vdd d+ d- *vddq
cywb022xx family document number: 001-13805 rev. *m page 8 of 78 packages and in terface options astoria provides one 100-ball vfbga, one 100-ball bga, one 1 21-ball fbga and two types of 81-ball wlcsp packages. the two wlcsp packages are sp wlcsp and lite sp wlcsp. these two pa ckages have different interf ace options as listed in ta b l e 5 . the 100-ball vfbga/bga package pin list is listed in table 6 on page 9 , the 81-ball sp csp package is listed in table 10 on page 21 , and the 81-ball lite sp csp package in table 11 on page 24 . table 5. interface options for 100-ball vfbga, 81-ball sp, and 81-ball lite sp package p-port s-port clock pcram sram adm pnan d i 2 c spi sd1 sd2 gpif gpio ext clk crystal freq. (mhz) 100-ball bga / vfbga ? ??????????? 19.2, 24, 26, 48 121-ball fbga ? ??????????? 19.2, 24, 26, 48 81-ball sp wlcsp ???????? 19.2, 26 81-ball lite sp wlcsp ???? ? ??? 26
cywb022xx family document number: 001-13805 rev. *m page 9 of 78 pin assignments table 6. astoria 100-ball vfbga package pin assignments pin name pin description power domain p-port ball # pcram non-multiplexing i/o address / data bus multiplexing (adm) i/o sram i/o pnand i/o spi i/o j2 clk (pull low in asyn mode) i clk (pull low in async mode) i ext pull low i ext pull low i sck i clock pvddq vgnd g1ce#ice#ice#ice#iss# ice# or spi slave select h3 a7 i ext pull up i a7 i a7 > 1:sbd a7 > 0:lbd i ext pull up i addr. bus 7 h2 a6 i sda i a6 i sda i/o sda i/o a6 or i 2 c data h1 a5 i scl i a5 i scl i/o scl i/o a5 or i 2 c clock j3 a4 i ext pull up i a4 i wp# i ext pull up i a4 or pnand wp j1 a3 i a3 = 0 (ext pull low) i a3 i a3 = 0 (ext pull low) i a3 = 1 (ext pull up) i a3 k3 a2 i a2 = 1 (ext pull up) i a2 i a2 = 0 (ext pull low) i a2 = 0 (ext pull low) ia2 k2 a1 i ext pull up i a1 i rb# o ext pull up i a1 or pnand r/b# k1 a0 i ext pull up i a0 i cle i ext pull up i a0 or pnand cle g2 dq[15] i/o ad[15] i/o dq[15] i/o i/o[15] i/o ext pull up i d15, ad15, or i/o15 g3 dq[14] i/o ad[14] i/o dq[14] i/o i/o[14] i/o ext pull up i d14, ad14, or i/o14 f1 dq[13] i/o ad[13] i/o dq[13] i/o i/o[13] i/o ext pull up i d13, ad13, or i/o13 f2 dq[12] i/o ad[12] i/o dq[12] i/o i/o[12] i/o ext pull up i d12, ad12, or i/o12 f3 dq[11] i/o ad[11] i/o dq[11] i/o i/o[11] i/o ext pull up i d11, ad11, or i/o11 e1 dq[10] i/o ad[10] i/o dq[10] i/o i/o[10] i/o ext pull up i d10, ad10, or i/o10 e2 dq[9] i/o ad[9] i/o dq[9] i/o i/o[9] i/o ext pull up i d9, ad9, or i/o9 e3 dq[8] i/o ad[8] i/o dq[8] i/o i/o[8] i/o ext pull up i d8, ad8, or i/o8 d1 dq[7] i/o ad[7] i/o dq[7] i/o i/o[7] i/o ext pull up i d7, ad7, or i/o7 d2 dq[6] i/o ad[6] i/o dq[6] i/o i/o[6] i/o ext pull up i d6, ad6, or i/o6 d3 dq[5] i/o ad[5] i/o dq[5] i/o i/o[5] i/o ext pull up i d5, ad5, or i/o5 c1 dq[4] i/o ad[4] i/o dq[4] i/o i/o[4] i/o ext pull up i d4, ad4, or i/o4 c2 dq[3] i/o ad[3] i/o dq[3] i/o i/o[3] i/o ext pull up i d3, ad3, or i/o3 c3 dq[2] i/o ad[2] i/o dq[2] i/o i/o[2] i/o ext pull up i d2, ad2, or i/o2 b1 dq[1] i/o ad[1] i/o dq[1] i/o i/o[1] i/o sdo o spi sdo, ad1or d1 b2 dq[0] i/o ad[0] i/o dq[0] i/o i/o[0] i/o sdi i spi sdi, ad0, or d0 a1 adv# i adv# i i ale i ext pull up i address valid b3 oe# i oe# i oe# i re# i ext pull up i output enable a2 we# i we# i we# i we# i ext pull up i we# drq & int a3 int# o int# o int# o int# o sint# o int request gvddq vgnd a4 drq# o drq# o drq# o drq# o n/c o dma request b4 dack# i dack# i dack# i dack# i ext pull up i dma acknowledgement u-port a5 d+ i/o/z usb d+ uvddq uvssq a6 d? i/o/z usb d? a7 swd+ i/o/z usb switch dp c6 swd? i/o/z usb switch dm
cywb022xx family document number: 001-13805 rev. *m page 10 of 78 s-port ball # double sdio configuration i/o sdio & gpio configuration i/o gpio configuration i/o gpif configuration i/o gpif & gpio configuration i/o g9 sd_d[7] i/o sd_d[7] i/o pd[7] (gpio) i/o gpif_data[15] i/o pd[7] (gpio) i/o sd data or gpio or gpif data ssvddq vgnd g10 sd_d[6] i/o sd_d[6] i/o pd[6] (gpio) i/o gpif_data[14] i/o pd[6] (gpio) i/o sd data or gpio or gpif data f9 sd_d[5] i/o sd_d[5] i/o pd[5] (gpio) i/o gpif_data[13] i/o pd[5] (gpio) i/o sd data or gpio or gpif data f10 sd_d[4] i/o sd_d[4] i/o pd[4] (gpio) i/o gpif_data[12] i/o pd[4] (gpio) i/o sd data or gpio or gpif data e9 sd_d[3] i/o sd_d[3] i/o pd[3] (gpio) i/o gpif_data[11] i/o pd[3] (gpio) i/o sd data or gpio or gpif data e10 sd_d[2] i/o sd_d[2] i/o pd[2] (gpio) i/o gpif_data[10] i/o pd[2] (gpio) i/o sd data or gpio or gpif data d9 sd_d[1] i/o sd_d[1] i/o pd[1] (gpio) i/o gpif_data[9] i/o pd[1] (gpio) i/o sd data or gpio or gpif data d10 sd_d[0] i/o sd_d[0] i/o pd[0] (gpio) i/o gpif_data[8] i/o pd[0] (gpio) i/o sd data or gpio or gpif data f8 sd_clk o sd_clk o pc[7] (gpio) i/o pc[7] (gpio) i/o pc[7] (gpio) i/o sd clock or gpio g8 sd_cmd i/o sd_cmd i/o pc[3] (gpio) i/o pc[3] (gpio) i/o pc[3] (gpio) i/o sd cmd or gpio h8 sd_pow sd_pow pc[6] (gpio) i/o pc[6] (gpio) i/o pc[6] (gpio) i/o sd power or gpio h10 sd_wp i sd_wp i n/c n/c pc[5] (gpio) sd write protect k7 sd2_d[7] i/o pb[7] (gpio) i/o pb[7] (gpio) i/o gpif_data[7] i/o gpif_data[7] i/o sd2 data or gpio or gpif data snvddq vgnd k8 sd2_d[6] i/o pb[6] (gpio) i/o pb[6] (gpio) i/o gpif_data[6] i/o gpif_data[6] i/o sd2 data or gpio or gpif data j8 sd2_d[5] i/o pb[5] (gpio) i/o pb[5] (gpio) i/o gpif_data[5] i/o gpif_data[5] i/o sd2 data or gpio or gpif data k9 sd2_d[4] i/o pb[4] (gpio) i/o pb[4] (gpio) i/o gpif_data[4] i/o gpif_data[4] i/o sd2 data or gpio or gpif data j9 sd2_d[3] i/o pb[3] (gpio) i/o pb[3] (gpio) i/o gpif_data[3] i/o gpif_data[3] i/o sd2 data or gpio or gpif data h9 sd2_d[2] i/o pb[2] (gpio) i/o pb[2] (gpio) i/o gpif_data[2] i/o gpif_data[2] i/o sd2 data or gpio or gpif data k10 sd2_d[1] i/o pb[1] (gpio) i/o pb[1] (gpio) i/o gpif_data[1] i/o gpif_data[1] i/o sd2 data or gpio or gpif data j10 sd2_d[0] i/o pb[0] (gpio) i/o pb[0] (gpio) i/o gpif_data[0] i/o gpif_data[0] i/o sd2 data or gpio or gpif data k6 sd2_clk o pa[6] (gpio) i/o pa[6] (gpio) i/o pa[6] (gpio) i/o pa[6] (gpio) i/o sd2 clock or gpio j6 sd2_cmd i/o pa[7] (gpio) i/o pa[7] (gpio) i/o pa[7] (gpio) i/o pa[7] (gpio) i/o sd2 cmd or gpio j5 sd2_pow o pc[0] (gpio) i/o pc[0] (gpio) i/o pc[0] (gpio) i/o pc[0] (gpio) i/o sd2 power or gpio k4 n/c o n/c o n/c o gpif_ctl[1] o gpif_ctl[1] o gpif control signal h6 n/c o n/c o n/c o gpif_ctl[0] o gpif_ctl[0] o gpif control signal j7 pa[5] (gpio) i/o pa[5] (gpio) i/o pa[5] (gpio) i/o pa[5] (gpio) i/o pa[5] (gpio) i/o gpio j4 n/c i n/c i n/c i gpif_rdy[0] o gpif_rdy[0] o gpif ready signal k5 sd2_wp o pc[2] (gpio) i/o pc[2] (gpio) i/o pc[2] (gpio) i/o pc[2] (gpio) i/o sd write protect or gpio other b10 resetout o resetout o resetout o resetout / gpif_rdy[1] o resetout / gpif_rdy[1] o reset out gvddq vgnd c9 sd2_cd i/o i pc-5 (gpio[1]) i/o pc-5 (gpio[1]) i/o pc-5 (gpio[1]) i/o pc-5 (gpio[1]) i/o gpio or sd2 cd d8 pc-4 (gpio[0]) or sd_cd i/o i pc-4 (gpio[0]) or sd_cd i/o i pc-4 (gpio[0]) i/o pc-4 (gpio[0]) i/o pc-4 (gpio[0]) i/o gpio or sd cd c10 reset# i reset c7 wakeup i wake up signal table 6. astoria 100-ball vfbga package pin assignments (continued) pin name pin description power domain
cywb022xx family document number: 001-13805 rev. *m page 11 of 78 conf c5 xtalslc[1] i clock select 1 gvddq vgnd c4 xtalslc[0] clock select 0 e8 test[2] i test cfg 2 c8 test[1] test cfg 1 d7 test[0] test cfg 0 clock a8 xtalin i crystal/clock in xvddq vgnd b8 xtalout o crystal out power d4, h4 pvddq power processor i/f vdd h5 snvddq power gpif vdd b5 uvddq power usb vdd h7 ssvddq power sdio vdd d6 gvddq power misc i/o vdd b9 avddq power analog vdd b7 xvddq power crystal vdd d5, g4, g5, g6, g7, f7 vdd power core vdd a10 vdd33 power independent 3.3 v b6 uvssq power usb gnd a9 avssq power analog gnd e4, e5, e6, e7, f4, f5, f6 vgnd power core gnd table 6. astoria 100-ball vfbga package pin assignments (continued) pin name pin description power domain
cywb022xx family document number: 001-13805 rev. *m page 12 of 78 table 7. astoria cywb0224abs 121-b all fbga package pin assignments pin name pin description power domain p-port ball # pcram non multiplexing i/o addr/data bus multiplexing (adm) i/o sram i/o pnand i/o spi i/o j2 clk (pull-low in asyn mode) i clk (pull-low in async mode) i ext pull-low i ext pull-low i sck i clock pvddq vgnd g1ce#ice#ice#ice#iss# ice# or spi slave select h3 a7 i ext pull-up i a7 i a7 > 1:sbd a7 > 0: lbd i ext pull-up i addr. bus 7 h2 a6 i sda i a6 i sda i/o sda i/o a6 or i 2 c data h1 a5 i scl i a5 i scl i/o scl i/o a5 or i 2 c clock j3 a4 i ext pull-up i a4 i wp# i ext pull-up i a4 or pnand wp j1 a3 i a3 = 0 (ext pull-low) ia3 ia3 = 0 (ext pull-low) i a3 = 1 (ext pull-up) i a3 k3 a2 i a2 = 1 (ext pull-up) i a2 i a2 = 0 (ext pull-low) i a2 = 0 (ext pull-low) ia2 k2 a1 i ext pull-up i a1 i rb# o ext pull-up i a1 or pnand r/b# k1 a0 i ext pull-up i a0 i cle i ext pull-up i a0 or pnand cle g2 dq[15] i/o ad[15] i/o dq[15] i/o i/o[15] i/o ext pull-up i d15, ad15, or i/o15 g3 dq[14] i/o ad[14] i/o dq[14] i/o i/o[14] i/o ext pull-up i d14, ad14, or i/o14 f1 dq[13] i/o ad[13] i/o dq[13] i/o i/o[13] i/o ext pull-up i d13, ad13, or i/o13 f2 dq[12] i/o ad[12] i/o dq[12] i/o i/o[12] i/o ext pull-up i d12, ad12, or i/o12 f3 dq[11] i/o ad[11] i/o dq[11] i/o i/o[11] i/o ext pull-up i d11, ad11, or i/o11 e1 dq[10] i/o ad[10] i/o dq[10] i/o i/o[10] i/o ext pull-up i d10, ad10, or i/o10 e2 dq[9] i/o ad[9] i/o dq[9] i/o i/o[9] i/o ext pull-up i d9, ad9, or i/o9 e3 dq[8] i/o ad[8] i/o dq[8] i/o i/o[8] i/o ext pull-up i d8, ad8, or i/o8 d1 dq[7] i/o ad[7] i/o dq[7] i/o i/o[7] i/o ext pull-up i d7, ad7, or i/o7 d2 dq[6] i/o ad[6] i/o dq[6] i/o i/o[6] i/o ext pull-up i d6, ad6, or i/o6 d3 dq[5] i/o ad[5] i/o dq[5] i/o i/o[5] i/o ext pull-up i d5, ad5, or i/o5 c1 dq[4] i/o ad[4] i/o dq[4] i/o i/o[4] i/o ext pull-up i d4, ad4, or i/o4 c2 dq[3] i/o ad[3] i/o dq[3] i/o i/o[3] i/o ext pull-up i d3, ad3, or i/o3 c3 dq[2] i/o ad[2] i/o dq[2] i/o i/o[2] i/o ext pull-up i d2, ad2, or i/o2 b1 dq[1] i/o ad[1] i/o dq[1] i/o i/o[1] i/o sdo o spi sdo, ad1or d1 b2 dq[0] i/o ad[0] i/o dq[0] i/o i/o[0] i/o sdi i spi sdi, ad0, or d0 a1 adv# i adv# i i ale i ext pull-up i address valid b3 oe# i oe# i oe# i re# i ext pull-up i output enable a2 we# i we# i we# i we# i ext pull-up i we# drq & int a3 int# o int# o int# o int# o sint# o int request gvddq vgnd a4 drq# o drq# o drq# o drq# o n/c o dma request b4 dack# i dack# i dack# i dack# i ext pull-up i dma acknowledgement u-port a5 d+ i/o/z usb d+ uvddq uvssq a6 d? i/o/z usb d? a7 swd+ i/o/z usb switch dp c6 swd? i/o/z usb switch dm
cywb022xx family document number: 001-13805 rev. *m page 13 of 78 s-port ball # double sdio configuration i/o sdio & gpio configuration i/o gpio configuration i/o gpif configuration i/o gpif & gpio configuration i/o g9 sd_d[7] i/o sd_d[7] i/o pd[7] (gpio) i/o gpif_data[15] i/o pd[7] (gpio) i/o sd data or gpio or gpif data ssvddq vgnd g10 sd_d[6] i/o sd_d[6] i/o pd[6] (gpio) i/o gpif_data[14] i/o pd[6] (gpio) i/o sd data or gpio or gpif data f9 sd_d[5] i/o sd_d[5] i/o pd[5] (gpio) i/o gpif_data[13] i/o pd[5] (gpio) i/o sd data or gpio or gpif data f10 sd_d[4] i/o sd_d[4] i/o pd[4] (gpio) i/o gpif_data[12] i/o pd[4] (gpio) i/o sd data or gpio or gpif data e9 sd_d[3] i/o sd_d[3] i/o pd[3] (gpio) i/o gpif_data[11] i/o pd[3] (gpio) i/o sd data or gpio or gpif data e10 sd_d[2] i/o sd_d[2] i/o pd[2] (gpio) i/o gpif_data[10] i/o pd[2] (gpio) i/o sd data or gpio or gpif data d9 sd_d[1] i/o sd_d[1] i/o pd[1] (gpio) i/o gpif_data[9] i/o pd[1] (gpio) i/o sd data or gpio or gpif data d10 sd_d[0] i/o sd_d[0] i/o pd[0] (gpio) i/o gpif_data[8] i/o pd[0] (gpio) i/o sd data or gpio or gpif data f8 sd_clk o sd_clk o pc[7] (gpio) i/o pc[7] (gpio) i/o pc[7] (gpio) i/o sd clock or gpio g8 sd_cmd i/o sd_cmd i/o pc[3] (gpio) i/o pc[3] (gpio) i/o pc[3] (gpio) i/o sd cmd or gpio h8 sd_pow sd_pow pc[6] (gpio) i/o pc[6] (gpio) i/o pc[6] (gpio) i/o sd power or gpio h10 sd_wp i sd_wp i n/c i n/c pc[5] (gpio) sd write protect k7 sd2_d[7] i/o pb[7] (gpio) i/o pb[7] (gpio) i/o gpif_data[7] i/o gpif_data[7] i/o sd2 data or gpio or gpif data snvddq vgnd k8 sd2_d[6] i/o pb[6] (gpio) i/o pb[6] (gpio) i/o gpif_data[6] i/o gpif_data[6] i/o sd2 data or gpio or gpif data j8 sd2_d[5] i/o pb[5] (gpio) i/o pb[5] (gpio) i/o gpif_data[5] i/o gpif_data[5] i/o sd2 data or gpio or gpif data k9 sd2_d[4] i/o pb[4] (gpio) i/o pb[4] (gpio) i/o gpif_data[4] i/o gpif_data[4] i/o sd2 data or gpio or gpif data j9 sd2_d[3] i/o pb[3] (gpio) i/o pb[3] (gpio) i/o gpif_data[3] i/o gpif_data[3] i/o sd2 data or gpio or gpif data h9 sd2_d[2] i/o pb[2] (gpio) i/o pb[2] (gpio) i/o gpif_data[2] i/o gpif_data[2] i/o sd2 data or gpio or gpif data k10 sd2_d[1] i/o pb[1] (gpio) i/o pb[1] (gpio) i/o gpif_data[1] i/o gpif_data[1] i/o sd2 data or gpio or gpif data j10 sd2_d[0] i/o pb[0] (gpio) i/o pb[0] (gpio) i/o gpif_data[0] i/o gpif_data[0] i/o sd2 data or gpio or gpif data k6 sd2_clk o pa[6] (gpio) i/o pa[6] (gpio) i/o pa[6] (gpio) i/o pa[6] (gpio) i/o sd2 clock or gpio j6 sd2_cmd i/o pa[7] (gpio) i/o pa[7] (gpio) i/o pa[7] (gpio) i/o pa [7] (gpio) i/o sd2 cmd or gpio j5 sd2_pow o pc[0] (gpio) i/o pc[0] (gpio) i/o pc[0] (gpio) i/o pc[0] (gpio) i/o sd2 power or gpio k4 n/c o n/c o n/c o gpif_ctl[1] o gpif_ctl[1] o gpif control signal h6 n/c o n/c o n/c o gpif_ctl[0] o gpif_ctl[0] o gpif control signal j7 pa[5] (gpio) i/o pa[5] (gpio) i/o pa[5] (gpio) i/o pa[5] (gpio) i/o pa[5] (gpio) i/o gpio j4 n/c i n/c i n/c i gpif_rdy[0] o gpif_rdy[0] o gpif ready signal k5 sd2_wp o pc[2] (gpio) i/o pc[2] (gpio) i/o pc[2] (gpio) i/o pc[2] (gpio) i/o sd write protect or gpio other b10 resetout o resetout o resetout o resetout / gpif_rdy[1] o resetout / gpif_rdy[1] o resetout gvddq vgnd c9 sd2_cd i/o i pc-5 (gpio[1]) i/o pc-5 (gpio[1]) i/o pc-5 (gpio[1]) i/o pc-5 (gpio[1]) i/o gpio or sd2 cd d8 pc-4 (gpio[0]) or sd_cd i/o i pc-4 (gpio[0]) or sd_cd i/o i pc-4 (gpio[0]) i/o pc-4 (gpio[0]) i/o pc-4 (gpio[0]) i/o gpio or sd cd c10 reset# i reset c7 wakeup i wake up signal table 7. astoria cywb0224abs 121-b all fbga package pin assignments (continued) pin name pin description power domain
cywb022xx family document number: 001-13805 rev. *m page 14 of 78 conf c5 xtalslc[1] i clock select 1 gvddq vgnd c4 xtalslc[0] clock select 0 e8 test[2] i test cfg 2 c8 test[1] test cfg 1 d7 test[0] test cfg 0 clock a8 xtalin i crystal / clock in xvddq vgnd b8 xtalout o crystal out power d4 h4 pvddq power processor i/f vdd h5 snvddq power gpif vdd b5 uvddq power usb vdd h7 ssvddq power sdio vdd d6 gvddq power misc i/o vdd b9 avddq power analog vdd b7 xvddq power crystal vdd d5, g4, g5, g6, g7, f7 vdd power core vdd a10 vdd33 power independent 3.3 v b6 uvssq power usb gnd a9 avssq power analog gnd e4, e5, e6, e7, f4, f5, f6 vgnd power core gnd table 7. astoria cywb0224abs 121-b all fbga package pin assignments (continued) pin name pin description power domain
cywb022xx family document number: 001-13805 rev. *m page 15 of 78 table 8. astoria cywb0220abs 121-b all fbga package pin assignments pin name pin description power domain p-port ball # pcram non multiplexing i/o addr/data bus multiplexing (adm) i/o sram i/o pnand i/o spi i/o j2 clk (pull-low in asyn mode) i clk (pull-low in async mode) i ext pull-low i ext pull-low i sck i clock pvddq vgnd g1 ce# i ce# i ce# i ce# i ss# i ce# or spi slave select h3 a7 i ext pull-up i a7 i a7 > 1:sbd a7 > 0: lbd i ext pull-up i addr. bus 7 h2 a6 i sda i a6 i sda i/o sda i/o a6 or i 2 c data h1 a5 i scl i a5 i scl i/o scl i/o a5 or i 2 c clock j3 a4 i ext pull-up i a4 i wp# i ext pull-up i a4 or pnand wp j1 a3 i a3 = 0 (ext pull-low) i a3 i a3 = 0 (ext pull-low) i a3 = 1 (ext pull-up) i a3 k3 a2 i a2 = 1 (ext pull-up) i a2 i a2 = 0 (ext pull-low) i a2 = 0 (ext pull-low) ia2 k2 a1 i ext pull-up i a1 i rb# o ext pull-up i a1 or pnand r/b# k1 a0 i ext pull-up i a0 i cle i ext pull-up i a0 or pnand cle g2 dq[15] i/o ad[15] i/o dq[15] i/o i/o[15] i/o ext pull-up i d15, ad15, or i/o15 g3 dq[14] i/o ad[14] i/o dq[14] i/o i/o[14] i/o ext pull-up i d14, ad14, or i/o14 f1 dq[13] i/o ad[13] i/o dq[13] i/o i/o[13] i/o ext pull-up i d13, ad13, or i/o13 f2 dq[12] i/o ad[12] i/o dq[12] i/o i/o[12] i/o ext pull-up i d12, ad12, or i/o12 f3 dq[11] i/o ad[11] i/o dq[11] i/o i/o[11] i/o ext pull-up i d11, ad11, or i/o11 e1 dq[10] i/o ad[10] i/o dq[10] i/o i/o[10] i/o ext pull-up i d10, ad10, or i/o10 e2 dq[9] i/o ad[9] i/o dq[9] i/o i/o[9] i/o ext pull-up i d9, ad9, or i/o9 e3 dq[8] i/o ad[8] i/o dq[8] i/o i/o[8] i/o ext pull-up i d8, ad8, or i/o8 d1 dq[7] i/o ad[7] i/o dq[7] i/o i/o[7] i/o ext pull-up i d7, ad7, or i/o7 d2 dq[6] i/o ad[6] i/o dq[6] i/o i/o[6] i/o ext pull-up i d6, ad6, or i/o6 d3 dq[5] i/o ad[5] i/o dq[5] i/o i/o[5] i/o ext pull-up i d5, ad5, or i/o5 c1 dq[4] i/o ad[4] i/o dq[4] i/o i/o[4] i/o ext pull-up i d4, ad4, or i/o4 c2 dq[3] i/o ad[3] i/o dq[3] i/o i/o[3] i/o ext pull-up i d3, ad3, or i/o3 c3 dq[2] i/o ad[2] i/o dq[2] i/o i/o[2] i/o ext pull-up i d2, ad2, or i/o2 b1 dq[1] i/o ad[1] i/o dq[1] i/o i/o[1] i/o sdo o spi sdo, ad1or d1 b2 dq[0] i/o ad[0] i/o dq[0] i/o i/o[0] i/o sdi i spi sdi, ad0, or d0 a1 adv# i adv# i i ale i ext pull-up i address valid b3 oe# i oe# i oe# i re# i ext pull-up i output enable a2 we# i we# i we# i we# i ext pull-up i we# drq & int a3 int# o int# o int# o int# o sint# o int request gvddq vgnd a4 drq# o drq# o drq# o drq# o n/c o dma request b4 dack# i dack# i dack# i dack# i ext pull-up i dma acknowledgement
cywb022xx family document number: 001-13805 rev. *m page 16 of 78 s-port double sdio configuration i/o sdio & gpio configuration i/o gpio configuration i/o gpif configuration i/o gpif & gpio configuration i/o g9 sd_d[7] i/o sd_d[7] i/o pd[7] (gpio) i/o gpif_data[15] i/o pd[7] (gpio) i/o sd data or gpio or gpif data ssvddq vgnd g10 sd_d[6] i/o sd_d[6] i/o pd[6] (gpio) i/o gpif_data[14] i/o pd[6] (gpio) i/o sd data or gpio or gpif data f9 sd_d[5] i/o sd_d[5] i/o pd[5] (gpio) i/o gpif_data[13] i/o pd[5] (gpio) i/o sd data or gpio or gpif data f10 sd_d[4] i/o sd_d[4] i/o pd[4] (gpio) i/o gpif_data[12] i/o pd[4] (gpio) i/o sd data or gpio or gpif data e9 sd_d[3] i/o sd_d[3] i/o pd[3] (gpio) i/o gpif_data[11] i/o pd[3] (gpio) i/o sd data or gpio or gpif data e10 sd_d[2] i/o sd_d[2] i/o pd[2] (gpio) i/o gpif_data[10] i/o pd[2] (gpio) i/o sd data or gpio or gpif data d9 sd_d[1] i/o sd_d[1] i/o pd[1] (gpio) i/o gpif_data[9] i/o pd[1] (gpio) i/o sd data or gpio or gpif data d10 sd_d[0] i/o sd_d[0] i/o pd[0] (gpio) i/o gpif_data[8] i/o pd[0] (gpio) i/o sd data or gpio or gpif data f8 sd_clk o sd_clk o pc[7] (gpio) i/o pc[7] (g pio) i/o pc[7] (gpio) i/o sd clock or gpio g8 sd_cmd i/o sd_cmd i/o pc[3] (gpio) i/o pc[3] (gpio) i/o pc[3] (gpio) i/o sd cmd or gpio h8 sd_pow sd_pow pc[6] (gpio) i/o pc[6] (gpio) i/o pc[6] (gpio) i/o sd power or gpio h10 sd_wp i sd_wp i n/c n/c pc[5] (gpio) sd write protect k7 sd2_d[7] i/o pb[7] (gpio) i/o pb[7] (gpio) i/o gpif_data[7] i/o gpif_data[7] i/o sd2 data or gpio or gpif data snvddq vgnd k8 sd2_d[6] i/o pb[6] (gpio) i/o pb[6] (gpio) i/o gpif_data[6] i/o gpif_data[6] i/o sd2 data or gpio or gpif data j8 sd2_d[5] i/o pb[5] (gpio) i/o pb[5] (gpio) i/o gpif_data[5] i/o gpif_data[5] i/o sd2 data or gpio or gpif data k9 sd2_d[4] i/o pb[4] (gpio) i/o pb[4] (gpio) i/o gpif_data[4] i/o gpif_data[4] i/o sd2 data or gpio or gpif data j9 sd2_d[3] i/o pb[3] (gpio) i/o pb[3] (gpio) i/o gpif_data[3] i/o gpif_data[3] i/o sd2 data or gpio or gpif data h9 sd2_d[2] i/o pb[2] (gpio) i/o pb[2] (gpio) i/o gpif_data[2] i/o gpif_data[2] i/o sd2 data or gpio or gpif data k10 sd2_d[1] i/o pb[1] (gpio) i/o pb[1] (gpio) i/o gpif_data[1] i/o gpif_data[1] i/o sd2 data or gpio or gpif data j10 sd2_d[0] i/o pb[0] (gpio) i/o pb[0] (gpio) i/o gpif_data[0] i/o gpif_data[0] i/o sd2 data or gpio or gpif data k6 sd2_clk o pa[6] (gpio) i/o pa[6] (gpio) i/o pa[6] (gpio) i/o pa[6] (gpio) i/o sd2 clock or gpio j6 sd2_cmd i/o pa[7] (gpio) i/o pa[7] (gpio) i/o pa[7] (gpio) i/o pa[7] (gpio) i/o sd2 cmd or gpio j5 sd2_pow o pc[0] (gpio) i/o pc[0] (gpio) i/o pc[0] (gpio) i/o pc[0] (gpio) i/o sd2 power or gpio k4 n/c o n/c o n/c o gpif_ctl[1] o gpif_ctl[1] o gpif control signal h6 n/c o n/c o n/c o gpif_ctl[0] o gpif_ctl[0] o gpif control signal j7 pa[5] (gpio) i/o pa[5] (gpio) i/o pa[5] (gpio) i/o pa[5] (gpio) i/o pa[5] (gpio) i/o gpio j4 n/c i n/c i n/c i gpif_rdy[0] o gpif_rdy[0] o gpif ready signal k5 sd2_wp o pc[2] (gpio) i/o pc[2] (gpio) i/o pc[2] (gpio) i/o pc[2] (gpio) i/o sd write protect or gpio other b10 resetout o resetout o resetout o resetout / gpif_rdy[1] o resetout / gpif_rdy[1] o reset out gvddq vgnd c9 sd2_cd i/o i pc-5 (gpio[1]) i/o pc-5 (gpio[1]) i/o pc-5 (gpio[1]) i/o pc-5 (gpio[1]) i/o gpio or sd2 cd d8 pc-4 (gpio[0]) or sd_cd i/o i pc-4 (gpio[0]) or sd_cd i/o i pc-4 (gpio[0]) i/o pc-4 (gpio[0]) i/o pc-4 (gpio[0]) i/o gpio or sd cd c10 reset# i reset c7 wakeup i wake up signal table 8. astoria cywb0220abs 121-b all fbga package pin assignments (continued) pin name pin description power domain
cywb022xx family document number: 001-13805 rev. *m page 17 of 78 conf c5 xtalslc[1] i clock select 1 gvddq vgnd c4 xtalslc[0] clock select 0 e8 test[2] i test cfg 2 c8 test[1] test cfg 1 d7 test[0] test cfg 0 clock a8 xtalin i crystal / clock in xvddq vgnd b8 xtalout o crystal out power d4 h4 pvddq power processor i/f vdd h5 snvddq power gpif vdd b5 uvddq power usb vdd h7 ssvddq power sdio vdd d6 gvddq power misc i/o vdd b9 avddq power analog vdd b7 xvddq power crystal vdd d5, g4, g5, g6, g7, f7 vdd power core vdd a10 vdd33 power independent 3.3 v b6 uvssq power usb gnd a9 avssq power analog gnd e4, e5, e6, e7, f4, f5, f6 vgnd power core gnd table 8. astoria cywb0220abs 121-b all fbga package pin assignments (continued) pin name pin description power domain
cywb022xx family document number: 001-13805 rev. *m page 18 of 78 table 9. astoria cywb0216abs 121-b all fbga package pin assignments pin name pin description power domain unused pins ball # pull direction i/o j2 p/d i pull-down pvddq vgnd g1 p/u i pull-up h3 p/u i pull-up j3 p/u i pull-up j1 p/u i pull-up k3 p/d i pull-down k2 p/u i pull-up k1 p/u i pull-up g2 p/u i pull-up g3 p/u i pull-up f1 p/u i pull-up f2 p/u i pull-up f3 p/u i pull-up e1 p/u i pull-up e2 p/u i pull-up e3 p/u i pull-up d1 p/u i pull-up d2 p/u i pull-up d3 p/u i pull-up c1 p/u i pull-up c2 p/u i pull-up c3 p/u i pull-up b1 p/u o pull-up b2 p/u i pull-up a1 p/u i pull-up b3 p/u i pull-up a2 p/u i pull-up a3 n/c o no connect gvddq vgnd a4 n/c o no connect b4 p/u i pull-up i2c pins interface pins i/o pin description h2 sda i/o i 2 c data pvddq vgnd h1 scl i/o i 2 c clock u-port a5 d+ i/o/z usb d+ uvddq uvssq a6 d? i/o/z usb d? a7 swd+ i/o/z usb switch dp c6 swd? i/o/z usb switch dm
cywb022xx family document number: 001-13805 rev. *m page 19 of 78 s-port double sdio configuration i/o sdio & gpio configuration i/o gpio configuration i/o gpif configuration i/o gpif & gpio configuration i/o g9 sd_d[7] i/o sd_d[7] i/o pd[7] (gpio) i/o gpif_data[15] i/o pd[7] (gpio) i/o sd data or gpio or gpif data ssvddq vgnd g10 sd_d[6] i/o sd_d[6] i/o pd[6] (gpio) i/o gpif_data[14] i/o pd[6] (gpio) i/o sd data or gpio or gpif data f9 sd_d[5] i/o sd_d[5] i/o pd[5] (gpio) i/o gpif_data[13] i/o pd[5] (gpio) i/o sd data or gpio or gpif data f10 sd_d[4] i/o sd_d[4] i/o pd[4] (gpio) i/o gpif_data[12] i/o pd[4] (gpio) i/o sd data or gpio or gpif data e9 sd_d[3] i/o sd_d[3] i/o pd[3] (gpio) i/o gpif_data[11] i/o pd[3] (gpio) i/o sd data or gpio or gpif data e10 sd_d[2] i/o sd_d[2] i/o pd[2] (gpio) i/o gpif_data[10] i/o pd[2] (gpio) i/o sd data or gpio or gpif data d9 sd_d[1] i/o sd_d[1] i/o pd[1] (gpio) i/o gpif_data[9] i/o pd[1] (gpio) i/o sd data or gpio or gpif data d10 sd_d[0] i/o sd_d[0] i/o pd[0] (gpio) i/o gpif_data[8] i/o pd[0] (gpio) i/o sd data or gpio or gpif data f8 sd_clk o sd_clk o pc[7] (gpio) i/o pc[7] (gpio) i/o pc[7] (gpio) i/o sd clock or gpio g8 sd_cmd i/o sd_cmd i/o pc[3] (gpio) i/o pc[3] (gpio) i/o pc[3] (gpio) i/o sd cmd or gpio h8 sd_pow sd_pow pc[6] (gpio) i/o pc[6] (gpio) i/o pc[6] (gpio) i/o sd power or gpio h10 sd_wp i sd_wp i n/c n/c pc[5] (gpio) sd write protect k7 sd2_d[7] i/o pb[7] (gpio) i/o pb[7] (gpio) i/o gpif_data[7] i/o gpif_data[7] i/o sd2 data or gpio or gpif data snvddq vgnd k8 sd2_d[6] i/o pb[6] (gpio) i/o pb[6] (gpio) i/o gpif_data[6] i/o gpif_data[6] i/o sd2 data or gpio or gpif data j8 sd2_d[5] i/o pb[5] (gpio) i/o pb[5] (gpio) i/o gpif_data[5] i/o gpif_data[5] i/o sd2 data or gpio or gpif data k9 sd2_d[4] i/o pb[4] (gpio) i/o pb[4] (gpio) i/o gpif_data[4] i/o gpif_data[4] i/o sd2 data or gpio or gpif data j9 sd2_d[3] i/o pb[3] (gpio) i/o pb[3] (gpio) i/o gpif_data[3] i/o gpif_data[3] i/o sd2 data or gpio or gpif data h9 sd2_d[2] i/o pb[2] (gpio) i/o pb[2] (gpio) i/o gpif_data[2] i/o gpif_data[2] i/o sd2 data or gpio or gpif data k10 sd2_d[1] i/o pb[1] (gpio) i/o pb[1] (gpio) i/o gpif_data[1] i/o gpif_data[1] i/o sd2 data or gpio or gpif data j10 sd2_d[0] i/o pb[0] (gpio) i/o pb[0] (gpio) i/o gpif_data[0] i/o gpif_data[0] i/o sd2 data or gpio or gpif data k6 sd2_clk o pa[6] (gpio) i/o pa[6] (gpio) i/o pa[6] (gpio) i/o pa[6] (gpio) i/o sd2 clock or gpio j6 sd2_cmd i/o pa[7] (gpio) i/o pa[7] (gpio) i/o pa[7] (gpio) i/o pa[7] (gpio) i/o sd2 cmd or gpio j5 sd2_pow o pc[0] (gpio) i/o pc[0] (gpio) i/o pc[0] (gpio) i/o pc[0] (gpio) i/o sd2 power or gpio k4 n/c o n/c o n/c o gpif_ctl[1] o gpif_ctl[1] o gpif control signal h6 n/c o n/c o n/c o gpif_ctl[0] o gpif_ctl[0] o gpif control signal j7 pa[5] (gpio) i/o pa[5] (gpio) i/o pa[5] (gpio) i/o pa[5] (gpio) i/o pa[5] (gpio) i/o gpio j4 n/c i n/c i n/c i gpif_rdy[0] o gpif_rdy[0] o gpif ready signal k5 sd2_wp o pc[2] (gpio) i/o pc[2] (gpio) i/o pc[2] (gpio) i/o pc[2] (gpio) i/o sd write protect or gpio other b10 resetout o resetout o resetout o resetout / gpif_rdy[1] o resetout / gpif_rdy[1] o reset out gvddq vgnd c9 sd2_cd i/o i pc-5 (gpio[1]) i/o pc-5 (gpio[1]) i/o pc-5 (gpio[1]) i/o pc-5 (gpio[1]) i/o gpio or sd2 cd d8 pc-4 (gpio[0]) or sd_cd i/o i pc-4 (gpio[0]) or sd_cd i/o i pc-4 (gpio[0]) i/o pc-4 (gpio[0]) i/o pc-4 (gpio[0]) i/o gpio or sd cd c10 reset# i reset c7 wakeup i wake up signal table 9. astoria cywb0216abs 121-b all fbga package pin assignments (continued) pin name pin description power domain
cywb022xx family document number: 001-13805 rev. *m page 20 of 78 conf c5 xtalslc[1] i clock select 1 gvddq vgnd c4 xtalslc[0] clock select 0 e8 test[2] i test cfg 2 c8 test[1] test cfg 1 d7 test[0] test cfg 0 clock a8 xtalin i crystal/clock in xvddq vgnd b8 xtalout o crystal out power d4 h4 pvddq power processor i/f vdd h5 snvddq power nand vdd b5 uvddq power usb vdd h7 ssvddq power sdio vdd d6 gvddq power misc i/o vdd b9 avddq power analog vdd b7 xvddq power crystal vdd d5, g4, g5, g6, g7, f7 vdd power core vdd a10 vdd33 power independent 3.3 v b6 uvssq power usb gnd a9 avssq power analog gnd e4, e5, e6, e7, f4, f5, f6 vgnd power core gnd table 9. astoria cywb0216abs 121-b all fbga package pin assignments (continued) pin name pin description power domain
cywb022xx family document number: 001-13805 rev. *m page 21 of 78 table 10. astoria 81-ball sp wlcsp package pin assignments pin name pin description power domain p-port ball # pnand i/o spi i/o h9 ext pull low i sck i clock pvddq vgnd f9 ce# i ss# i ce# or spi slave select e7 sda i/o sda i/o i2c data h8 scl i/o scl i/o i2c clock j9 wp# i ext pull up i pnand wp g8 a[3]=0; (ext pull low) i a[3]=0; (ext pull up) i a[3] e6 a[2]=0; (ext pull low) i a[2]=0; (ext pull low) i a[2] g9 rb# o ext pull up i pnand r/b# f8 cle i ext pull up i pnand cle d9 i/o[7] i/o ext pull up i io7 d8 i/o[6] i/o ext pull up i io6 c9 i/o[5] i/o ext pull up i io5 b9 i/o[4] i/o ext pull up i io4 c8 i/o[3] i/o ext pull up i io3 c7 i/o[2] i/o ext pull up i io2 b8 i/o[1] i/o sdo o io1 or spi sdo a8 i/o[0] i/o sdi i io0 or spi sdi b7 ale i ext pull up i address valid b6 re# i ext pull up i output enable a7 we# i ext pull up i we# int c1 int# o sint# o int request gvddq vgnd u-port a4 d+ i/o/z usb d+ uvddq uvssq a5 d? i/o/z usb d? c4 swd+ i/o/z usb switch d+ c5 swd? i/o/z usb switch d?
cywb022xx family document number: 001-13805 rev. *m page 22 of 78 s-port ball # double sdio configuration i/o sdio & gpio configuration i/o gpio configuration i/o gpif configuration i/o gpif & gpio configuration i/o h2 sd_d[7] i/o sd_d[7] i/o pd[7] (gpio) i/o gpif_data [15] i/o pd[7] (gpio) i/o sd data or gpio or gpif data ssvddq vgnd h1 sd_d[6] i/o sd_d[6] i/o pd[6] (gpio) i/o gpif_data [14] i/o pd[6] (gpio) i/o sd data or gpio or gpif data g3 sd_d[5] i/o sd_d[5] i/o pd[5] (gpio) i/o gpif_data [13] i/o pd[5] (gpio) i/o sd data or gpio or gpif data g2 sd_d[4] i/o sd_d[4] i/o pd[4] (gpio) i/o gpif_data [12] i/o pd[4] (gpio) i/o sd data or gpio or gpif data f2 sd_d[3] i/o sd_d[3] i/o pd[3] (gpio) i/o gpif_data [11] i/o pd[3] (gpio) i/o sd data or gpio or gpif data f3 sd_d[2] i/o sd_d[2] i/o pd[2] (gpio) i/o gpif_data [10] i/o pd[2] (gpio) i/o sd data or gpio or gpif data e3 sd_d[1] i/o sd_d[1] i/o pd[1] (gpio) i/o gpif_data [9] i/o pd[1] (gpio) i/o sd data or gpio or gpif data e2 sd_d[0] i/o sd_d[0] i/o pd[0] (gpio) i/o gpif_data [8] i/o pd[0] (gpio) i/o sd data or gpio or gpif data g1 sd_clk o sd_clk pc-7 (gpio) i/o pc-7 (gpio) i/o pc-7 (gpio) i/o sd clock or gpio f4 sd_cmd i/o sd_cmd i/o pc-3 (gpio) i/o pc-3 (gpio) i/o pc-3 (gpio) i/o sd cmd or gpio j1 sd_pow o sd_pow o pc-6 (gpio) i/o pc-6 (gpio) i/o pc-6 (gpio) i/o sd power or gpio e1 sd_wp i sd_w i n/c i n/c i pc-5 (gpio) i/o sd write protect h5 sd2_d[7] i/o pb[7] (gpio) i/o pb[7] (gpio) i/o gpif_data [7] i/o gpif_data [7] i/o sd2 data or gpio or gpif data snvddq vgnd j4 sd2_d[6] i/o pb[6] (gpio) i/o pb[6] (gpio) i/o gpif_data [6] i/o gpif_data [6] i/o sd2 data or gpio or gpif data g5 sd2_d[5] i/o pb[5] (gpio) i/o pb[5] (gpio) i/o gpif_data [5] i/o gpif_data [5] i/o sd2 data or gpio or gpif data h4 sd2_d[4] i/o pb[4] (gpio) i/o pb[4] (gpio) i/o gpif_data [4] i/o gpif_data [4] i/o sd2 data or gpio or gpif data j3 sd2_d[3] i/o pb[3] (gpio) i/o pb[3] (gpio) i/o gpif_data [3] i/o gpif_data [3] i/o sd2 data or gpio or gpif data g4 sd2_d[2] i/o pb[2] (gpio) i/o pb[2] (gpio) i/o gpif_data [2] i/o gpif_data [2] i/o sd2 data or gpio or gpif data h3 sd2_d[1] i/o pb[1] (gpio) i/o pb[1] (gpio) i/o gpif_data [1] i/o gpif_data [1] i/o sd2 data or gpio or gpif data j2 sd2_d[0] i/o pb[0] (gpio) i/o pb[0] (gpio) i/o gpif_data [0] i/o gpif_data [0] i/o sd2 data or gpio or gpif data f7 sd2_clk o pa[6] (gpio) i/o pa[6] (gpio) i/o pa-6 (gpio) i/o pa-6 (gpio) i/o sd2 clock or gpio h6 sd2_cmd i/o pa[7] (gpio) i/o pa[7] (gpio) i/o pa-7 (gpio) i/o pa-7 (gpio) i/o sd2 cmd or gpio g7 sd2_pow o pc[0] (gpio) i/o pc[0] (gpio) i/o pc-0 (gpio) i/o pc-0 (gpio) i/o sd2 power or gpio j8 n/c o n/c o n/c o gpif_ctl[1] o gpif_ctl[1] o gpif control signal j5 n/c o n/c o n/c o gpif_ctl[0] o gpif_ctl[0] o gpif control signal g6 pa-5 (gpio) i/o pa-5 (gpio) i/o pa-5 (gpio) i/o pa-5 (gpio) i/o pa-5 (gpio) i/o gpio h7 n/c i n/c i n/c i gpif_rdy[0] o gpif_rdy[0] o gpif ready signal j7 sd2_wp o pc-2 (gpio) i/o pc-2 (gpio) i/o pc-2 (gpio) i/o pc-2 (gpio) i/o sd write protect or gpio other c2 resetout o resetout o resetout o resetout / gpif_rdy[1] o resetout / gpif_rdy[1] o resetout or gpif gvddq vgnd d2 pc-5 (gpio[1]) or sd2_cd i/o pc-5 (gpio[1]) i/o pc-5 (gpio[1]) i/o pc-5 (gpio[1]) i/o pc-5 (gpio[1]) i/o gpio or sd2 cd d1 pc-4 (gpio[0]) or sd_cd i/o i pc-4 (gpio[0]) or sd_cd i/o i pc-4 (gpio[0]) i/o pc-4 (gpio[0]) i/o pc-4 (gpio[0]) i/o gpio or sd cd c3 reset# i reset d4 wakeup i wake up signal table 10. astoria 81-ball sp wlcsp package pin assignments (continued) pin name pin description power domain
cywb022xx family document number: 001-13805 rev. *m page 23 of 78 conf a1 xtalslc i clock select gvddq vgnd b1 test[2] i test cfg 2 c6 test[1] i test cfg 1 b4 test[0] i test cfg 0 clk a2 xtalin i crystal / clock in xvddq vgnd power a9, e8 pvddq power processor i/f vdd j6 snvddq power gpif vdd b5 uvddq power usb vdd f1 ssvddq power sdio vdd d3 gvddq power misc i/o vdd b3 avddq power analog vdd a6, d6, e5, f6 vdd power core vdd a3 uvssq power usb gnd b2 avssq power analog gnd d5, d7, e4, e9, f5 vgnd power core gnd table 10. astoria 81-ball sp wlcsp package pin assignments (continued) pin name pin description power domain
cywb022xx family document number: 001-13805 rev. *m page 24 of 78 table 11. astoria 81-ball lite sp wlcsp package pin assignments pin name pin description power domain p-port ball # sram interface adm (address/data multi- plexing) i/o pnand i/o g9 ce# i ce# i ce# i ce# pvddq vgnd h5 a7 i external pull up i a7 > 1:sbd a7 > 0: lbd ia7 j8 a6 i sda i/o sda i/o a7 or sda h6 a5 i scl i/o scl i/o a6 or scl h7 a4 i external pull up i wp# i a4 or wp# j9 a3 i external pull low i external pull low i a3 h8 a2 i external pull up i external pull low i a2 h9 a1 i external pull up i r/b# i a1 or r/b# g8 a0 i external pull up i cle i a0 or cle g6 dq[15] i/o ad[15] i/o i/o[15] i/o d15, ad15, or io15 f9 dq[14] i/o ad[14] i/o i/o[14] i/o d14, ad14, or io14 f8 dq[13] i/o ad[13] i/o i/o[13] i/o d13, ad13, or io13 f7 dq[12] i/o ad[12] i/o i/o[12] i/o d12, ad12, or io12 e9 dq[11] i/o ad[11] i/o i/o[11] i/o d11, ad11, or io11 e8 dq[10] i/o ad[10] i/o i/o[10] i/o d10, ad10, or io10 d9 dq[9] i/o ad[9] i/o i/o[9] i/o d9, ad9, or io9 d7 dq[8] i/o ad[8 i/o i/o[8] i/o d8, ad8, or io8 d8 dq[7] i/o ad[7] i/o i/o[7] i/o d7, ad7, or io7 c9 dq[6] i/o ad[6] i/o i/o[6] i/o d6, ad6, or io6 d6 dq[5] i/o ad[5] i/o i/o[5] i/o d5, ad5, or io5 b9 dq[4] i/o ad[4] i/o i/o[4] i/o d4, ad4, or io4 c8 dq[3] i/o ad[3] i/o i/o[3] i/o d3, ad3, or io3 c7 dq[2] i/o ad[2] i/o i/o[2] i/o d2, ad2, or io2 b8 dq[1] i/o ad[1] i/o i/o[1] i/o d1, ad1, or io1 a8 dq[0] i/o ad[0] i/o i/o[0] i/o d0i, ad0, or io0 b7 i adv# i ale i address valid b6 oe# i oe# i re# i output enable a7 we# i we# i we# i we# int c1 int# o int# o int# o int request gvddq vgnd d4 drq# o drq# o drq# o dma request d3 dack# i dack# i dack# i dma ack u-port a4 d+ i/o/z usb d+ uvddq uvssq a5 d? i/o/z usb d? c4 swd+ i/o/z usb switch dp c5 swd? i/o/z usb switch dm
cywb022xx family document number: 001-13805 rev. *m page 25 of 78 s-port s-port interface i/o f3 sd_d[7] i/o sd data or gpio ssvddq vgnd h1 sd_d[6] i/o sd data or gpio g2 sd_d[5] i/o sd data or pio e3 sd_d[4] i/o sd data or gpio f2 sd_d[3] i/o sd data or gpio f1 sd_d[2] i/o sd data or gpio e2 sd_d[1] i/o sd data or gpio e1 sd_d[0] i/o sd data or gpio g1 sd_clk i/o sd clock or gpio j1 sd_cmd i/o sd cmd or gpio j5 pb[7] (gpio) i/o gpioi j4 pb[6] (gpio) i/o gpioi h4 pb[5] (gpio) i/o gpioi j3 pb[4] (gpio) i/o gpioi h3 pb[3] (gpio) i/o gpioi g4 pb[2] (gpio) i/o gpioi j2 pb[1] (gpio) i/o gpioi h2 pb[0] (gpio) i/o gpioi j7 gpif_rdy o test mode j6 gpif_ctl i test mode (ext pull-high) other d1 sd_cd i sd cd gvddq vgnd c2 reset# i reset e5 wakeup i wake up signal conf c3 test[2] i test cfg 2 gvddq vgnd d5 test[1] itest cfg 1 b1 test[0] itest cfg 0 clk a2 xtalin i clock in xvddq vgnd a1 xtalout o clock out power a9, f6 pvddq power processor i/f vdd b5 uvddq power usbvdd e4 ssvddq power sdio vdd d2 gvddq power misc i/o vdd b3 avddq power analog vdd b4 xvddq power crystal vdd e7, a6, c6, f5 vdd power core vdd a3 uvssq power usb gnd b2 avssq power analog gnd g7, e6, g5, f4, g3 vgnd power core gnd table 11. astoria 81-ball lite sp wlcsp package pin assignments (continued)
cywb022xx family document number: 001-13805 rev. *m page 26 of 78 figure 9. astoria 100-ball vfbga ball map - top view 123 4 5 6 7 8 9 10 aadv# ? we# ? int# ? drq# ? d+ ? d \? swd+ ? xtalin ? avssq ? vdd33 a bdq[1] dq[0] ? oe# ? dack# ? uvddq ? uvssq ? xvddq ? xtalout ? avddq ? resetout b cdq[4] ? dq[3] dq[2] ? xtalslc[0] ? xtalslc[1] ? swd \? wakeup ? test[1] ? gpio[1] ? reset# c ddq[7] ? dq[6] ? dq[5] ? pvddq ? vdd ? gvddq ? test[0] ? gpio[0] ? sd_d[1] sd_d[0] d e dq[10] dq[9] ? dq[8] ? vgnd ? vgnd ? vgnd ? vgnd ? test[2] ? sd_d[3] sd_d[2] e f dq[13] dq[12] ? dq[11] ? vgnd ? vgnd ? vgnd ? vdd ? sd_clk ? sd_d[5] ? sd_d[4] f gce# ? dq[15] ? dq[14] ? vdd ? vdd ? vdd ? vdd ? sd_cmd ? sd_d[7] ? sd_d[6] g ha[5] ? a[6] ? a[7] ? pvddq ? snvddq gpif_ctl[0] ssvddq ? sd_pow ? gpif_data[2] sd_wp h ja[3] ? clk ? a[4] gpif_rdy[0] pc[0] pa[7] pa[5] gpif_data[5] gpif_data[3] gpif_data[0] j ka[0] ? a[1] ? a[2] ? gpif_ctl[1] pc[2] pa[6] gpif_data[7] gpif_data[6] gpif_data[4] gpif_data[1] k 123 4 5 6 7 8 9 10 gvdd q ssvdd q vddq/avddq vgnd/avssq snvdd q power ? domain ? key uvdd q uvss q pvddq xvddq vdd33
cywb022xx family document number: 001-13805 rev. *m page 27 of 78 figure 10. ball map_cywb0216 - top view 1234567891011 a p/ u p/u n/c n/c d+ d- swd+ xtalin avssq v dd33 n/c a b p/ u p/ u p/ u p/ u uv ddq uv ssq xv ddq xta lout a v ddq resetout n/c b c p/ u p/ u p/ u xta l sl c[ 0 ] xta l sl c[ 1 ] swd- wakeup test[1] gpio[1] reset# n/c c d p/u p/u p/u pv ddq v dd gv ddq test[0] gpio[0] sd_d[1] sd_d[0] n/c d e p/ u p/ u p/ u vgnd vgnd vgnd vgnd test[2] sd_d[3] sd_d[2] n/c e f p/ u p/ u p/ u vgnd vgnd vgnd v dd sd_clk sd_d[5] sd_d[4] n/c f g p/u p/u p/u v dd v dd v dd v dd sd_cmd sd_d[7] sd_d[6] n/c g h scl sda p/u pv ddq snv ddq gpif_ctl [0] ssv ddq sd_pow gpif_da ta [2] sd_wp n/c h j p/u p/d p/u gpif_rdy [0] pc [0] pa [7] pa [5] gpif_data[5] gpif_data[3] gpif_data[0] n/c j k p/u p/u p/d gpif_ctl [1] pc [2] pa [6] gpif_data[7] gpif_data[6] gpif_data[4] gpif_data[1] n/c k l n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c l 1234567891011 uv ddq uvssq gv ddq ssv ddq vddq/avddq vgndavssq pv ddq snv ddq xv ddq vdd33 p/u p/d n/c top view power dom ain key
cywb022xx family document number: 001-13805 rev. *m page 28 of 78 figure 11. ball map_cywb0220 - top view 1234567891011 a adv# we# int# drq# n/c n/c n/c xta lin avssq v dd33 n/c a b dq[1] dq[0] oe# da ck# uv ddq uv ssq xv ddq xta lout a v ddq resetout n/c b c dq[4] dq[3] dq[2] xtalslc[0] xtalslc[1] n/c wakeup test[1] gpio[1] reset# n/c c d dq[7] dq[6] dq[5] pv ddq v dd gv ddq test[0] gpio[0] sd_d[1] sd_d[0] n/c d e dq[10] dq[9] dq[8] vgnd vgnd vgnd vgnd test[2] sd_d[3] sd_d[2] n/c e f dq[13] dq[12] dq[11] vgnd vgnd vgnd v dd sd_clk sd_d[5] sd_d[4] n/c f g ce# dq[15] dq[14] v dd v dd v dd v dd sd_cmd sd_d[7] sd_d[6] n/c g h a [5] a [6] a [7] pv ddq snv ddq gpif_ctl[0] ssv ddq sd_pow gpif_da ta [2] sd_wp n/c h j a[3] clk a[4] gpif_rdy[0] pc [0] pa [7] pa[5] gpif_data[5] gpif_data[3] gpif_data[0] n/c j k a[0] a[1] a[2] gpif_ctl[1] pc [2] pa [6] gpif_data[7] gpif_data[6] gpif_data[4] gpif_data[1] n/c k l n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c l 1234567891011 uv ddq uvssq gv ddq ssv ddq vddq/avddq vgndavssq pv ddq snv ddq xv ddq vdd33 n/c top view power dom ain key
cywb022xx family document number: 001-13805 rev. *m page 29 of 78 figure 12. ball map_cywb0224 - top view 1234567891011 a adv# we# int# drq# d+ d- swd+ xtalin avssq v dd33 n/c a b dq[1] dq[0] oe# da ck# uv ddq uv ssq xv ddq xta lout a v ddq resetout n/c b c dq[4] dq[3] dq[2] xtalslc[0] xtalslc[1] swd- wakeup test[1] gpio[1] reset# n/c c d dq[7] dq[6] dq[5] pv ddq v dd gv ddq test[0] gpio[0] sd_d[1] sd_d[0] n/c d e dq[10] dq[9] dq[8] vgnd vgnd vgnd vgnd test[2] sd_d[3] sd_d[2] n/c e f dq[13] dq[12] dq[11] vgnd vgnd vgnd v dd sd_clk sd_d[5] sd_d[4] n/c f g ce# dq[15] dq[14] v dd v dd v dd v dd sd_cmd sd_d[7] sd_d[6] n/c g h a[5] a[6] a[7] pvddq snvddq gpif_ctl [0] ssvddq sd_pow gpif_data[2] sd_wp n/c h j a[3] clk a[4] gpif_rdy[0] pc[0] pa[7] pa[5] gpif_data[5] gpif_data[3] gpif_data[0] n/c j k a [0] a [1] a [2] gpif_ctl[1] pc[2] pa [6] gpif_da ta [7] gpif_da ta [6] gpif_da ta [4] gpif_da ta [1] n/c k l n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c l 1234567891011 uv ddq uv ssq gv ddq ssv ddq vddq/avddq vgndavssq pvddq snv ddq xvddq vdd33 n/c top view power dom ain key
cywb022xx family document number: 001-13805 rev. *m page 30 of 78 figure 13. astoria 81-ball sp wlcsp ball map - top view 123456789 axtalslc ? xtalin ? uvssq ? d+ ? d \? vdd ? we# ? io[0] ? pvddq a btest[2] ? avssq ? avddq ? test[0] ? uvddq ? re# ? ale ? io[1] ? io[4] b cint# ? resetout ? reset# ? swd+ ? swd \? test[1] ? io[2] ? io[3] ? io[5] c dgpio[0] ? gpio[1] ? gvddq ? wakeup ? vgnd ? vdd ? vgnd ? io[6] ? io[7] d esd_wp ? sd_d[0] ? sd_d[1] ? vgnd ? vdd ? a[2] ? sda ? pvddq ? vgnd e f ssvddq ? sd_d[3] ? sd_d[2] ? sd_cmd ? vgnd ?? vdd pa[6] cle ? ce# f g sd_clk ? sd_d[4] ? sd_d[5] ? gpif_data[2] gpif_data[5] pa[5] pc[0] a[3] ? r/b# g h sd_d[6] ? sd_d[7] ? gpif_data[1] gpif_data[4] gpif_data[7] pa[7] gpif_rdy[0] scl ? pull \ low h jpow ? gpif_data[0] gpif_data[3] gpif_data[6] gpif_ctl ? [0] snvddq ? pc ? [2] gpif_ctl ? [1] wp# j 123456789 power ? domain ? key uvdd q uvss q gvdd q xvddq ssvddq vddq/avddq vgnd/avssq pvddq snvdd q
cywb022xx family document number: 001-13805 rev. *m page 31 of 78 figure 14. astoria 81-ball lite sp wlcsp ball map - top view 12 3 4 56789 a xtalout xtalin uv ssq d+ d- vdd we# dq[0] pvddq a b test[0] avssq a v ddq xv ddq uv ddq oe# a dv # dq[1] dq[4] b c int# reset# test[2] swd+ swd- v dd dq[2] dq[3] dq[6] c d gpio[0] gv ddq da ck# drq# test[1] dq[5] dq[8] dq[7] dq[9] d e sd_d[0] sd_d[1] sd_d[4] ssvddq wakeup vgnd vdd dq[10] dq[11] e f sd_d[2] sd_d[3] sd_d[7] vgnd vdd pvddq dq[12] dq[13] dq[14] f g sd_clk sd_d[5] vgnd pb[ 2 ] ( gpio) vgnd dq[15] vgnd a[0] ce# g h sd_d[6] pb[0] (gpio) pb[3] (gpio) pb[5] (gpio) a[7] a[5] a[4] a[2] a[1] h j sd_ cmd pb[ 1 ] ( gpio) pb[ 4 ] ( gpio) pb[ 6 ] ( gpio) pb[ 7 ] ( gpio) gpif_ rdy gpif_ ctl a [ 6 ] a [ 3 ] j 12 3 4 56789 vgnd/avssq pvddq xvddq power domain key uvddq uvssq gvddq ssvddq vdd/avddq
cywb022xx family document number: 001-13805 rev. *m page 32 of 78 absolute maximum ratings exceeding maximum ratings may s horten the useful life of the device. user guidelines are not tested. storage temperature ................................ ?65 c to +150 c ambient temperature with power supplied (industri al) ........................ ?40 c to +85 c supply voltage to ground potential vdd, avddq ..............................................?0.5 v to +2.0 v gvddq, pvddq, ssvddq, snvddq, uvddq, and vdd33 and xvddq ..............?0.5 v to +4.0 v dc input voltage to any input pin (depends on i/o supply voltage. inputs are not overvoltage tolerant.) ..............1.89 v to 3.6 v dc voltage applied to outputs in high z state .................... ?0.5 v to vddq + 0.5 v static discharge voltage (esd) from jesd22-a114 ...................................... > 2000 v latch up current ..................................................... > 200 ma maximum output shor t circuit current for all i/o configurations. (vout = 0 v) [1] ................. ?100 ma operating conditions t a (ambient temperature under bias) industrial .................................................... ?40 c to +85 c vdd, avddq supply voltage ..........................1.7 v to 1.9 v uvddq supply voltage ... .............. .............. .....3.0 v to 3.6 v pvddq, gvddq, snvddq, ssvddq supply voltage ..................................................1.7 v to 3.6 v xvddq (crystal i/o) supply voltage ...............3.0 v to 3.6 v xvddq (ext. clock i/o) supply voltage ..........1.7 v to 1.9 v note 1. do not test more than one output at a time. duration of the short circuit must not exceed one second. tested initially and af ter any design or process changes that may affect these parameters
cywb022xx family document number: 001-13805 rev. *m page 33 of 78 dc characteristics table 12. dc specifications for all voltage supplies (except usb switch) parameter description conditions min typ max unit v dd core voltage supply 1.7 1.8 1.9 v avddq analog voltage supply 1.7 1.8 1.9 v xvddq crystal voltage supply 3.0 3.3 3.6 v xvddq clock voltage supply 1.7 1.8 1.9 v pvddq [4] processor interface i/o 1.7 1.8, 2.5, 3.3 3.6 v gvddq [4] miscellaneous i/o voltage supply 1.7 1.8, 2.5, 3.3 3.6 v snvddq [3, 4] s-port gpif voltage supply 1.7 1.8, 2.5, 3.3 3.6 v ssvddq [3, 4] s-port sd i/o voltage supply 1.7 1.8, 2.5, 3.3 3.6 v uvddq [6] usb voltage supply 3.0 3.3 3.6 v vdd33 power sequence c ontrol supply 3.0 3.3 3.6 v v ih1 [5] input high voltage 1 all ports except usb, 2.0 v < v cc < 3.6 v 0.625 v cc ?v cc + 0.3 v v ih2 [5] input high voltage 2 a ll ports except usb, 1.7 v < v cc < 2.0 v v cc ? 0.4 ? v cc + 0.3 v il input low voltage ?0.3 ? 0.25 v cc v v oh output high voltage i oh (max) = ?0.1 ma 0.9 v cc ?v v ol output low voltage i ol (min) = 0.1 ma ? 0.1 v cc v i ix input leakage current all i/o signals held at vddq ?1 ? 1 ? a i oz output leakage current all i/o signals held at vddq ?1 ? 1 ? a i cc core operating current of core voltage supply (v dd ) and analog voltage supply (avddq) vfbga package outputs tri-stated ??110ma wlcsp package outputs tri-stated ??115ma i cc crystal operating current of crystal voltage supply (xvddq) [8] vfbga package xtalout floating ??5ma wlcsp package ? n/a i cc usb operating current of usb voltage supply (uvddq) [8] operating and terminated for high speed mode ??25ma i sb1 (for 100-ball vfbga and 81-ball sp wlcsp- packages) total standby current of astoria when device is in suspend mode 1. *vddq = 3.3 v nominal (3.0?3.6 v) 2. outputs and bidirs high or floating [7] 3. xtalout floating 4. d+ floating, d?grounded 5. device in suspend mode 25 ? c?300 [2] ? ? a 85 ? c ? ? 3000 ? a notes 2. isb1 typical value is not a maximum specification but a ty pical value. isb1 maximum current value specified for 85c. 3. the ssvddq i/o voltage can be dynamically c hanged (for example, from high range to lo w range) as long as the supply voltage u ndershoot does not surpass the lower minimum voltage limit. ssvddq and snvddq levels for sd modes: 2.0 v ? 3.6 v, mmc modes: 1.7 v ? 3.6 v. 4. interfaces with a voltage range are adjustable with respec t to the i/o voltage and supports multiple i/o voltages. 5. v cc = pertinent vddq value. 6. when u-port is in a disabled state, uvddq can go down to 2.4 v, provided uvddq is still the highest supply voltage level. 7. the outputs and bidirs that are forced low in standby mode can increase i/o supply standby current beyond specified value. 8. active current conditions: -uvddq: usb transmitting 50% of the time, receiving 50% of the time. -pvddq/snvddq/ssvddq/gvddq: active current depends on i/o activity, bus load and supply level. -xvddq: assume highest frequency cl ock (48 mhz) or crystal (26 mhz).
cywb022xx family document number: 001-13805 rev. *m page 34 of 78 i sb1 (for 81-ball lite sp wlcsp) total standby current of astoria when device is in suspend mode 6. *vddq = 3.3 v nominal (3.0?3.6 v) 7. outputs and bidirs high or floating [7] 8. xtalout floating 9. d+ floating, d? grounded 10.device in suspend mode 25 ? c tbd tbd tbd ? a 85 ? c tbd tbd tbd ? a i sb2 total standby current of astoria when device is in standby mode 1. *vddq = 3.3 v nominal (3.0?3.6 v) 2. outputs and bidirs high or floating [7] 3. xtalout floating 4. d+ floating, d? grounded 25 ? c? ? 52 ? a 85 ? c? ? 450 ? a i sb3 total standby current of astoria when device is in core power-down mode 1. outputs and bidirs high or floating [7] 2. xtalout floating 3. d+ floating, d? grounded 4. core powered down 25 ? c? ? 28 ? a 85 ? c? ? 139 ? a table 12. dc specifications for all voltage supplies (except usb switch) (continued) parameter description conditions min typ max unit table 13. usb switch dc specifications parameter description conditions min typ max unit v ih input voltage high 1.6 ? ? v v il input voltage low ? ? 0.8 v r on on resistance 4.5 7 10 ? r off off resistance 1m ? ? ? c dp/dm_on d+/d? on capacitance (with full-speed switch on) ? ? 25 pf c dp/dm_off d+/d? off capacitance ? ? 20 pf table 14. capacitance parameter description conditions typ max unit c in input pin capacitance, except d+/d? ta = 25 c, f = 1 mhz, v cc = v ccio ?9pf input pin capacitance, d+/d? ? 15 pf c out output pin capacitance ? 10 pf
cywb022xx family document number: 001-13805 rev. *m page 35 of 78 ac timing parameters p port interface pcram non multiplexing asynchronous mode table 15. asynchronous mode timing parameters parameter description min max unit read timing parameters interface bandwidth (mbps) ? 66.7 mbps taa address to data valid ? 30 ns toh data output hold from address change 3 ? ns tea chip enable to data valid ? 30 ns taadv adv# to data valid access time ? 30 ns tavs address valid to adv# high 5 ? ns tavh adv# high to address hold 2 [10] ?ns tcvs ce# low setup time to adv# high 5 ? ns tvph adv# high time 15 [9] ?ns tvp adv# pulse width low 7.5 ? ns toe oe# low to data valid ? 22.5 ns tolz oe# low to low z 3 ? ns tohz oe# high to high z 0 22.5 ns tlz ce# low to low z 3 ? ns thz ce# high to high z ? 22.5 ns write timing parameters tcw ce# low to write end 30 ? ns taw address valid to write end 30 ? ns tas address setup to write start 0 ? ns tadvs adv# setup to write start 0 ? ns twp we# pulse width 22 ? ns twph we# high time 10 ? ns tcph ce# high time 10 ? ns tavs address valid to adv# high 5 ? ns tavh adv# high to address hold 2 [10] ?ns tcvs ce# low setup time to adv# high 5 ? ns tvph adv# high time 15 [9] ?ns tvp adv# pulse width low 7.5 ? ns tvs adv# low to end of write 30 ? ns tdw data setup to write end 18 ? ns tdh data hold from write end 0 ? ns twhz write to dq high z output ? 22.5 ns tow end of write to low z output 3 ? ns notes 9. in applications where access cycle time is at least 60 ns, t vph can be relaxed to 12 ns. 10. in applications where back-to-back accesses are not performed on different endpoint addresses, the minimum t avh spec. can be relaxed to 0 ns.
cywb022xx family document number: 001-13805 rev. *m page 36 of 78 figure 15. non multiplexing asynchronous pseudo cram mode single read time parameters a adv# ce# oe # r/w# dq taa tea toe tolz tohz tlz thz valid address high-z tvph tavs tavh tvp valid output taadv toh tcvs figure 16. non multiplexing asyn chronous pseudo cram mode back to back read timing parameters a adv# ce# oe # we# dq taa tea tohz tlz thz high-z tvph tavs tavh tvp taadv valid address valid address valid output valid output
cywb022xx family document number: 001-13805 rev. *m page 37 of 78 figure 17. non multiplexing asynchronous pseudo cram mode back to back write timing parameters a adv# ce# oe # we# dq_in high-z tvph tavs tavh tvp valid address valid input valid input tdw tdh dq_out tvs tas twhz tlz valid address taw tcw tow twph twp tadvs tcph figure 18. non multiplexing as ynchronous pseudo cram mode r ead to write timing parameters a adv# ce# oe# we# dq_in high-z tvph tavs tavh tvp v alid add ress valid input va lid in put tdw tdh dq_out tvs tas twhz valid address taw tow twp taa toe tolz tlz high-z tvph tavs tavh tvp taad v valid addr ess valid output tohz tea
cywb022xx family document number: 001-13805 rev. *m page 38 of 78 address data multiplexing asynchronous mode figure 19. non multiplexing as ynchronous pseudo cram mode wr ite to read timing parameters a adv# ce# oe# we# dq_in tavs tavh tvp valid address valid input tdw tdh dq_out tvs tas twhz taw twp taa toe tolz tavs tavh tvp taadv valid addr ess valid output table 16. address data multiplexing asynchronous mode timing parameters parameter description min max unit read timing parameters interface bandwidth ? 50 mbps taa address to data valid ? 30 ns tea chip enable access time ? 30 ns taadv adv# to data valid access time ? 30 ns tavs address valid to adv# high 5 ? ns tavh adv# high to address hold 2 ? ns tcvs ce# low setup time to adv# high 5 ? ns tvph adv# high time 15 ? ns tvp adv# pulse width low 7.5 ? ns tavdoe adv# high to oe# low 0 ? ns toe oe# low to data valid ? 22.5 ns tolz oe# low to low z 3 ? ns tohz oe# high to high z ? 22.5 ns tlz ce# low to low z 3 ? ns thz ce# high to high z ? 22.5 ns write timing parameters tcw ce# low to write end 30 ? ns
cywb022xx family document number: 001-13805 rev. *m page 39 of 78 taw address valid to write end 30 ? ns tavdwe adv# high to write start 0 ? ns twp we# pulse width 22 ? ns tavs address valid to adv# high 5 ? ns tavh adv# high to address hold 2 ? ns tcvs ce# low setup time to adv# high 5 ? ns tvph adv# high time 15 ? ns tvp adv# pulse width low 7.5 ? ns tvs adv# low to end of write 30 ? ns tds data setup to write end 18 ? ns tdh data hold from write end 0 ? ns table 16. address data multiplexing asynchronous mode timing parameters (continued) parameter description min max unit figure 20. address data multiplexing asynchronous single read timing parameters a<7:0>/ dq<15:0> adv# ce# oe # we# valid data taa toe tolz tohz thz high-z tvph ta vs tavh tvp taadv valid addr ess tea tlz high-z logic high tavdoe tcvs
cywb022xx family document number: 001-13805 rev. *m page 40 of 78 non multiplexing synchronous mode timing parameters figure 21. address data multiplexing as ynchronous single write timing parameters table 17. non multiplexing synchronous mode timing parameters parameter description min max unit freq interface clock frequency ? 33 mhz tclk clock period 30 ? ns tclkh clock high time 12 ? ns tclkl clock low time 12 ? ns twh address hold time (write to the register) fo r the first time that processor configures the p-port from non-adm asynchronous mode to non-adm synchronous mode 0?ns ts ce#/we#/addr/dq setup time 7.5 ? ns th ce#/we#/addr/dq hold time 1.5 ? ns tco clock to valid data ? 18 ns toh clock to data hold time 2 ? ns tolz oe# low to data low z 3 ? ns tohz oe# high to data high z ? 22.5 ns toe oe# low to data valid ? 22.5 ns tckhz clock to data high z ? 18 ns tcklz clock to data low z 3 ? ns a<7:0>/ dq<15:0> adv# ce# we# taw twp tvph tavs tavh tvp valid address tcw high-z tavdwe valid input tds tdh t v s tcvs
cywb022xx family document number: 001-13805 rev. *m page 41 of 78 figure 22. non multiplexing synchronous pseudo cram mode writ e timing parameters a[7:0] ce# clk oe# ts th tclk dq[15:0] (input) we# tclkh tclkl an an+1 an+2 an+3 dq[15:0] (output) dn dn+1 dn+2 dn+3 high-z note: - assumes previous cycle had ce# deselected - oe# is don?t care during write operations twh figure 23. non multiplexing synchronous pseudo cram mode read timing parameters a[7:0] ce# clk oe# ts th tclk dq[15:0] (input) we# tclkh tclkl an an+1 an+2 an+3 dq[15:0] (output) dn dn+1 high-z note: - assumes previous cycle had ce # deselected an+4 high-z toh tco tcklz tohz tolz toe
cywb022xx family document number: 001-13805 rev. *m page 42 of 78 figure 24. non multiplexing synchronous mode read (oe# fixed low) timing parameters a[7:0] ce# clk oe # ts th we# ax ax+1 dq[15:0] (output) note: - ass umes previous s everal c ycles w ere read toh dx-1 dx-2 tco dx tc khz ax+2 dx dx+1 figure 25. non multiplexing synchronous mode read to write (oe# controlled) timing parameters a[7:0] ce# clk oe # ts th tclk dq[15:0] (input) we# tclkh tclkl ax ax+1 an an+1 dq[15:0] (output) high-z note: - assumes previous several cycles were read - (ax) and (ax+1) cycles are turnaround . (a x+1) operation does not cross pipeli ne . an+2 toh dn dn+1 tohz dx-1 dx-2 tco ts th dn+2 dx
cywb022xx family document number: 001-13805 rev. *m page 43 of 78 figure 26. non multiplexing synchronous mode read to write (oe# fixed low) timing parameters a[7:0] ce# clk oe# ts th tclk dq[15:0] (input) we# tclkh tclkl ax ax+1 ax+2 an dq[15:0] (output) high-z note: - assumes previous several cycles were read - in this scenario, oe# is held low - (ax) and (ax+1) cycles are turnaround. (ax+1) operation does not cross pipeline. - no operation is performed during the ax+2 cycle (true turnaround operation) an+1 toh dn dn+1 dx-1 dx-2 tco ts th tco dx figure 27. non multiplexing synchronous mode write to read timing parameters a[7:0] ce# clk oe# ts th tclk dq[15:0] (input) we# tclkh tclkl an an+1 an+2 an+3 dq[15:0] (output) dn dn+1 dn+2 dn+3 high-z note: - assumes previous cycle had ce# deselected - oe# is don?t care during write operations twh
cywb022xx family document number: 001-13805 rev. *m page 44 of 78 address data multiplexing synchronous mode table 18. address data multiplexing synchronous mode parameters parameter description min max unit freq interface clock frequency ? 33 mhz tavh address hold time (write to the register) for the first time that processor configures the p-port from adm asynchronous mode to adm synchronous mode 2?ns tclk clock period 30 ? ns tclkh clock high time 12 ? ns tclkl clock low time 12 ? ns ts ce#/we#/dq setup time 7.5 ? ns th ce#/we#/dq hold time 1.5 ? ns tco clock to valid data ? 18 ns toh clock to data hold time 2 ? ns tavdoe adv# high to oe# low 0 ? ns tavdwe adv# high to we# low 0 ? ns thz ce# high to data high z ? 22.5 ns tohz oe# high to data high z ? 22.5 ns tolz oe# low to data low z 3 ? ns toe oe# low to data valid ? 22.5 ns figure 28. address data multiplexing synchronous burst read timing parameters (burst of 4 with latency=2, we#=high) a<7:0>/ dq<15:0> adv# ce# oe# we# tavdoe ts valid address logic high ts d0 d1 th ts th toh tco d2 d3 thz tohz tclkh tclkl tclk tolz clk toe tavh * * tavh is the adm address hold time (write to the register) for the fi rst time that processor configure the p-port astoria from adm async mode to adm sync mode
cywb022xx family document number: 001-13805 rev. *m page 45 of 78 figure 29. address data multiplexing synchronous burst write timing parameters (burst of 4 with latency=2, oe# is ignored) a<7:0>/ dq<15:0> adv# ce# we# tavdwe ts valid address ts d1 th ts th tdh tds d2 d3 tdh tclkh tclkl tclk ts clk d0 tavh * * tavh is the adm address hold time (write to the re gister) for the first time that processor configure the p-port astoria from adm async mode to adm sync mode table 19. asynchronous sram mode timing parameters parameter description min max unit interface bandwidth (mbps) ? 66.7 mbps read timing parameters trc read cycle time 30 ? ns taa address to data valid ? 30 ns toh data output hold from address change 3 ? ns tea chip enable to data valid ? 30 ns toe oe# low to data valid ? 22.5 ns tolz oe# low to low z 3 ? ns tohz oe# high to high z 0 22.5 ns tlz ce# low to low z 3 ? ns thz ce# high to high z ? 22.5 ns write timing parameters twc write cycle time 30 ? ns tcw ce# low to write end 30 ? ns taw address valid to we# end 30 ? ns tas address setup to we# or ce# start 0 ? ns
cywb022xx family document number: 001-13805 rev. *m page 46 of 78 non multiplexing asynchronous sram mode tah address hold time from we# or ce# end for pcram to sram changes (astoria is default in the pcram mode after reset. this timing is the requirement for the first time to access the p-port interface config uration register to change the astoria to psram mode) 2?ns address hold time from we# or ce# end for psram mode 0 ? twp we# pulse width 22 ? ns twph we# high time 10 ? ns tcph ce# high time 10 ? ns tds data setup to write end 18 ? ns tdh data hold from write end 0 ? ns twhz write to dq high z output ? 22.5 ns tow end of write to low z output 3 ? ns tdpw drq# pulse width 110 ? ns table 19. asynchronous sram mode timing parameters (continued) parameter description min max unit figure 30. non multiplexing asynch ronous sram read timing parameters trc taa toh trc tea toe tolz tohz thz tlz address data out dat a valid previous data valid address ce# oe# data out dat a valid high impedance high impedance endpoint read ? address transition controlled timing (oe# is asserted ) oe # controlled timing
cywb022xx family document number: 001-13805 rev. *m page 47 of 78 figure 31. non multiplexing asynchronous sram write timing (we# and ce# controlled) write cycle 2 ce# controlled , oe# high during w rite twc tcw taw tas tah tds tdh twhz valid data address data i/o twp ce# we# oe # write cycle 1 we# controlled, oe# high during write twph valid data twc tcw taw tas tah tds tdh twhz valid data address data i/o twp ce# we# oe # tcph valid data
cywb022xx family document number: 001-13805 rev. *m page 48 of 78 pseudo nand (pnand) mode figure 32. non multiplexing asynchronous sram write timing (we# controlled, oe# low) twc tcw taw tas tah tds tdh valid data ce# we# data i/o twp tow twhz write cycle 3 we# controlled. oe# low table 20. pnand mode parameters parameter description min max unit tadl address to data loading time non lna mode register write 100 ? ns non lna mode ep write 100 ? ns lna mode 450 ? ns talh ale hold time 5?ns tals ale setup time 15 ? ns tar ale to re# delay 10 ? ns tbers block erase time mcu/s-port nand dependent tcea ce# access time ? 35 ns tch ce# hold time 5?ns tchz ce# high to o/p hi-z ? 40 ns tclh cle hold time 5?ns tclr cle to re# time 10 ? ns tcls cle setup time 15 ? ns tcs ce# setup time 20 ? ns tdh data hold time 5?ns tds data setup time 15 ? ns toh data output hold time 15 ? ns
cywb022xx family document number: 001-13805 rev. *m page 49 of 78 tprog program time for lna mode depends on mcu/s-port/nand ns program time for register write in non lna mode 130 ? ns program time for ep write in non lna mode 130 ? ns tr busy duration during non lna register read using page read 130 ? ns busy duration during non lna ep read using page read 130 ? ns busy duration during lna page read (sbd/sld) depends on mcu/s-port/nand ns trc read cycle time (vfbga package) 30 ? ns read cycle time (wlcsp package) 33 ? trea re# for register access time ? 30 ns re# for ep access time ? 30 ns treh re# high hold time 10 ? ns trhw re# high to we low 40 ? ns trhz re# high to output high z ? 40 ns trp re# pulse width 15 ? ns trr ready to re low 20 ? ns trst device reset time depends on mcu/s-port/nand ns twb we# high to busy ? 100 ns twc write cycle time (vfbga package) 30 ? ns write cycle time (wlcsp package) 33 ? twh we# high hold time 10 ? ns twhr we# high to re low in non lna mode 30 ? ns we# high to re low in lna mode 450 ? ns twp we# pulse width 15 ? ns table 20. pnand mode parameters (continued) parameter description min max unit figure 33. pnand mode command latch cycle cle ce# we# ale i/ox tcls tclh tcs tch twp tals talh tds tdh command
cywb022xx family document number: 001-13805 rev. *m page 50 of 78 figure 34. pnand mode address latch cycle tcls tcs twc twc twc twc twp twp twp twp tals tals tals tals talh twh twh twh twh tdh t a l s tds tds tdh tds tdh td s tdh tds tdh talh talh talh talh cle ce# we# ale i/ox col.add2 row.add1 row.add2 row.add3 col.add1 figure 35. pnand mode input data latch cycle twp twp twp twh tds tds tds tdh tdh tdh din 0 din 1 din final twc tals tclh tch cle ce# ale we# i/ox
cywb022xx family document number: 001-13805 rev. *m page 51 of 78 figure 36. pnand mode serial access cycle after read treh trr trc trea trea trea trhz dout dout dout trhz toh tcea tchz toh ce# re# i/ox r/ b # figure 37. pnand mode status read cycle tcls tclr tcs twp tds tdh trea twhr tcea tir trhz tchz toh toh 70h status output tclh cle ce# we # re# i/ox
cywb022xx family document number: 001-13805 rev. *m page 52 of 78 figure 38. pnand lbd read operation tr trr twc trc trhz tar twb busy tclr 00h col add1 col add2 row ad d1 row add2 row add3 30h dout n dout n+1 dout m column address row address cle ce# we# ale re# i/ox r/b# trp table 21. page-read command sequence for large-block devices cycle type io bus comments cmd0 00h page-read command - 1 st cycle ca0 ep_offset[7:0]/ reg_addr[7:0] reg_sel field determines how the two co lumn address cycles are interpreted ep_offset[11:10] = reg_sel = 2`b11 ? register ep_offset[11:10] = reg_sel = 2`b0x, 2`b10 ?ep buffer offset ep_offset[11:0] = ep buffer offset ca1 {4?b0000, ep_offset[11:8]} ra0 row address byte 0 f irst row-address cycle ra0[4:0] = default epa ? endpoint address ra1 row address byte 1 the number row-address bytes present in page-read command depend on ra_count configuration parameter setting. lna row addresses are interpreted by firmware; ra2 row address byte 2 ra3 row address byte 3 cmd1 30h page-read command - 2 nd cycle data[0-2111] data data is returned by astoria delay tr beyond the second command.
cywb022xx family document number: 001-13805 rev. *m page 53 of 78 figure 39. pnand lbd read operation ca0 ca1 epa[4:0] ep_offset[11:8] ep_offset[7:0]/ reg_addr[7:0] 0 7 reg_sel[1:0] ra0 (default epa position) reserved ra1 ra2 ra3 figure 40. pnand sbd read operation tr trr twc trc trhz twb busy 00h, 01h, or *50h col add1 row add1 row add2 row add3 dout n dout n+ 1 dout m column address row address cle ce# we# ale re# i/ox r/b# trp * for t he c ommand 50h, a[3:0] in col add1 are valid address and a [7:4] are don?t c are tar
cywb022xx family document number: 001-13805 rev. *m page 54 of 78 figure 41. small block device mode address cycles table 22. page-read command se quence for small-block devices cycle type io bus comments cmd0 00h/01h/50h sets base-address within page as 0, 256, or 512, for read operation. ca0 ep_offset[7:0]/ reg_addr[7:0] ep_offset[7:0] = ep buffer of fset for non-register accesses. reg_addr[7:0] specifies register address when epa[4:0] field = 5`b10000. ra0 row address byte 0 first row-address cycle ra0[4:0] = default epa ? endpoint address epa may be specified in any other row-address byte. ra1 row address byte 1 the number row-address bytes present in page-read command depend on ra_count configuration parameter setting. lna row addresses are interpreted by firmware; ra2 row address byte 2 ra3 row address byte 3 data[0-527] data data is returned by astoria delay tr beyond the second command. ca0 ep_offset[7:0]/ reg_addr[6:0] 0 7 ra1 ra0 - default epa position ra2 ra3 epa[4:0]
cywb022xx family document number: 001-13805 rev. *m page 55 of 78 figure 42. pnand mode lbd ra ndom data operation (casdo) trc tr tc lr twhr twb tar trr trea busy 00h col add1 row add1 30h dout n dout n+ 1 05h e0h dout m col add2 row add2 row add3 col add1 col add2 dout m+1 column address row address column address cle ale i/ox we # r/b# ce# re# trp trhw figure 43. pnand mode register read using casdo in 8-bit mode tclr twhr trea 05h e0h col add1 col add2 column address cle ale i/ox we# r/b# ce# re# dout1 *dout2 * this timing diagram shows the 8-bit register read. for 16-bit register read, dout2 is not available tch
cywb022xx family document number: 001-13805 rev. *m page 56 of 78 figure 44. pnand mode lbd read operation (with ce# don?t care) cle ale i/ox we# r/b# ce# twb busy column address row address re# 00h col add1 col add2 row add1 row add2 row add3 30h d out n dout n+1 t r dout m dout i/ox ce# re# tcea trea
cywb022xx family document number: 001-13805 rev. *m page 57 of 78 figure 45. pnand mode sbd read operation (with ce# don?t care) cle ale i/ox we# r/b# ce# column address row address re# 00h col add1 row add1 row add2 row add3 twb busy d out n dout n+1 t r dout m d out i/ox ce# re# tcea trea
cywb022xx family document number: 001-13805 rev. *m page 58 of 78 figure 46. pnand mode lbd page program operation twb 80h col add1 row add1 col add2 row add2 row add3 column address row address tprog twc tadl serial data input command din n din m 10 h 70h i/o0 1 up to m byte serial input program command m = 2112byte in 8-bit interface m = 1056 in 16-bit interface i/o0=0 successful pr ogram i/o0=1 error in program note: tadl is the time from we rising edge of final address cycle to the we rising edge of first data cycle read status command cle ale i/ox we# r/b# ce# re# twhr
cywb022xx family document number: 001-13805 rev. *m page 59 of 78 figure 47. pnand mode s bd page program operation 80h col add1 row add1 row add2 column address row address tprog twc tadl serial data input command din n din m 10h 70h i/o 0 1 up to m byte serial input pr ogr am command m = 528 byte in 8-bit interface m = 264 byte in 16-bit interface i/o0=0 successful program i/o0=1 error in program read status command cle ale i/ox we# r/b# ce# re# row add3 twb
cywb022xx family document number: 001-13805 rev. *m page 60 of 78 figure 48. pnand mode lbd page program op eration with random data input (casdi) twb 80h col add1 row add1 col add2 row add2 row add3 column address row address tprog twc serial data input command din j din k 70h i/o0 read status command tadl din n din m col add2 col add1 10h serial input program command random data input command column address serial input 85h cle ale i/ox ce# we# re# r/b# twhr *random programming (casdi) to endpoint is only supported during logical nand em ulation (lna mode) of lbd device. partial page programming is not supported figure 49. pnand mode register write usin g casdi in 8-bit mode tadl din1 *din2 col add1 random data input command serial input 85h cle ale i/ox ce# we# re# r/b# col add2 * this timing diagram shows the 8-bit register write. for 16-bit register write, din2 should not be available twc
cywb022xx family document number: 001-13805 rev. *m page 61 of 78 figure 50. pnand mode lbd page progr am operation (with ce# don?t care) twb 80h col add1 row add1 col add2 row add2 row add3 column address row address tprog twc tadl serial data input command din n din m 10h 70h i/o0 1 up to m byte serial input pr ogr am command m = 2112 byte in 8-bit interface m = 1056 byte in 16-bit interface i/o0=0 successful program i/o0=1 error in program note: tadl is the time from we rising edge of final address cycle to the we rising edge of first data cycle read status command cle ale i/ox we# r/b# ce# re# twhr ce# we# tcs twp tch
cywb022xx family document number: 001-13805 rev. *m page 62 of 78 figure 51. pnand mode sbd page pr ogram operation (with ce# don?t care) 80h col add1 row add1 row add2 column address row address tprog twc tadl serial data input command din n din m 10h 70h i/o 0 1 up to m byte serial input program command m = 528 byte in 8-bit interface m = 264 byte in 16-bit interface i/o0=0 successful program i/o0=1 error in program read status command cle ale i/ox we# r/b# ce# re# row add3 twb ce# we# tcs twp tch
cywb022xx family document number: 001-13805 rev. *m page 63 of 78 figure 52. pnand mode block erase operation twc 60h row add2 row add1 row add3 d0h 70h i/o 0 busy auto block er ase setup command row address read status command i/o0=0 successful erase i/o0=1 error in erase erase command twb tbers cle ale i/ox r/b# re# we# ce# figure 53. pnand mode multi-blocks (up to 4) erase 60 h row add2 row add1 row add3 d0h 70h i/o 0 busy auto block erase setup command row address r e ad s tatus command i/o 0= 0 successful erase i/o0=1 error in erase er a se c o mm a nd twb tbers cle ale i/ox r/b# re# we# ce# tw c 60h row add2 row ad d 1 row ad d 3 d0h auto block erase setup command row address erase command 4 th block erase 1 st block erase 2 nd and 3 rd blo ck er a se note: the multi-block erase can support up to 4 blocks erase
cywb022xx family document number: 001-13805 rev. *m page 64 of 78 figure 54. pnand mode read id operation 90h cle ale we# i/ox re# ce# tar trea byte 0 read id command address 1cycle byte 1 byte 2 byte 3 byte 4 byte 5 byte 0 ? byte 5 are the values of registers of pnad_rd_id0 to pnand_rd_id5. can up to six bytes 00h figure 55. pnand mode read id2 operation 91h 00h cle ale we# i/ox re# ce# tar trea ext_id read id command address 1cycle
cywb022xx family document number: 001-13805 rev. *m page 65 of 78 spi and pi2c interface figure 56. pnand mode reset operation twb trst cle ce# we # r/ b # i/ox ffh table 23. spi mode parameters parameter description min max units f op operating frequency 0 26 mhz t cyc cycle time 38.5 ? ns t lead enable lead time 19.23 ? ns t lag enable lag time 19.23 ? ns t sckh clock high time 17.33 ? ns t sckl clock low time 17.33 ns t su data setup time (inputs) ? 7 ns t h data hold time (inputs) ? 7 ns t v data valid time, after enable edge ? 18 ns t ho data hold time, after enable edge 0 ? ns
cywb022xx family document number: 001-13805 rev. *m page 66 of 78 figure 57. spi timing diagram t cyc t sckh t sckl t lead t su t h t lag t v t ho ss# sck miso mosi (msb) bit-7 in bit-6 in (lsb) bit-0 in (msb) bit-7 out bit-6 out (lsb) bit-7 out note note: not defined but normal msb of character just received t ho table 24. pi2c interface standard mode parameters parameter description min max units f operating frequency 0 82 khz tbuf bus free time (between stop and start conditions) 4.7 ? s thd:sta hold time after (repeated) start condition. after this period the first clock is generated 4.0 ? s tsu:sta repeated start condition setup time 4.7 ? s tsu:sto stop condition setup time 4.0 ? s thd:dat data hold time 0?ns tsu:dat data setup time 250 ? ns ttimeout detect clock low timeout na ms tlow clock low period 4.7 ? s thigh clock high period 4.0 ? s tlow:sext cumulative clock low ex tend time (slave device) na ms t r rise time ? 1000 ns t f fall time ?300ns
cywb022xx family document number: 001-13805 rev. *m page 67 of 78 other p-port timings drq# min pulse width (tdpw): the minimum duration that drq# is deasserted following a drq acknowledgement (clear of dmaval) is 110 ns in async mode or five p-port clock (clk) cycles in sync mode. same register write-to-read holdoff (twrho): a read of a particular register must wait for a holdoff period following a write operation to that same regist er address to ensure that valid updated data is read. in async mode, this holdoff time is 150 ns. in sync mode, this holdoff time is seven p-port clock (clk) cycles. register update-to-read holdoff (turho): same status registers are updated as side effect from accesses to other registers. for example, clearin g the dmaval field automatically clears the associated endpoint buffer bit within the drq status register. a holdoff time must elapse from the first register access before the update is reflected in a subsequent read operation. this holdoff time is identical to the twrho. table 25. pi2c interface fast mode parameters parameter description min max units f operating frequency 0 312 khz tbuf bus free time (between stop and start condition) 1.3 ? s thd:sta hold time after (repeated) start condition. after this period the first clock is generated 0.6 ? s tsu:sta repeated start condition setup time 0.6 ? s tsu:sto stop condition setup time 0.6 ? s thd:dat data hold time 00.9ns tsu:dat data setup time 100 ? ns ttimeout detect clock low timeout na ms tlow clock low period 1.3 ? s thigh clock high period 0.6 ? s tlow:sext cumulative clock low ex tend time (slave device) na ms t r rise time ?300ns t f fall time ?300ns figure 58. pi2c timing diagram t f t r t hd;sta t low t hd;dat t su;dat t high t su;sta t buf t su;sto t hd;sta ssrs p sda scl 70% 30% 50% 50% 50% 70% 30%
cywb022xx family document number: 001-13805 rev. *m page 68 of 78 s port interface ac timing parameters sd/mmc/mmc+/ce-ata timing parameters for all conditions, sd/mmc data is driven and sampled on the rising edge of sd_clk. note that ce-ata electrical and timing parameters are equivalent to mmc. figure 59. sd/mmc/ce-ata timing waveform ? all modes sd_cmd/ sd_d0-d3 output sd_clk tsdclk tsdclkl sd_cmd/ sd_d0-d3 input tsdclkh tsdoh tsdos tsdih tsdis tsdckhz tsdcklz table 26. common timing parameters for sd/mmc/ce-ata ? during identification mode parameter description min max units sdfreq sd_clk interface clock frequency 0 400 khz tsdclk clock period 2.5 ? s tsdclkh clock high time 1.0 ? s tsdclkl clock low time 1.0 ? s table 27. common timing parameters for sd/mmc/ce-ata ? during data transfer mode parameter description min max units sdfreq sd_clk interface clock frequency 5 48 mhz tsdclk clock period 20.8 200 ns tsdclkod clock duty cycle 40 60 % tsclkr clock rise time ?3ns tsclkf clock fall time ?3ns table 28. timing parameters for sd ? all modes parameter description min max units tsdis input setup time 4 ? ns tsdih input hold time 2.5 ? ns tsdos output setup time 7 ? ns tsdoh output hold time 6 ? ns tsdckhz clock to data high z ? 18 ns tsdcklz clock to data low z 3 ? ns
cywb022xx family document number: 001-13805 rev. *m page 69 of 78 reset and standby timing parameters the astoria reset mechanism and the standby mode are described in this section. sleep time (tslp): the maximum time from deassertion of wakeup to when astoria enters low power state (sleep mode) is 1 ms. wakeup time (twu): the minimum time from assertion of wakeup pin (or initial power on with wakeup high) to when any register operation is conduct ed is 1 ms if an external clock is present, or 5 ms if a crystal is used. the cy_an_mem_pwr_magt_stat.wakeup field can only be polled after wakeup time following reset deassertion or wakeup assertion. minimum reset# pulse width (trpw): 5 ms when a crystal is used as clock or 1 ms when an external clock is used. minimum wakeup pulse width (twpw): 5 ms. minimum high on reset# a nd wakeup (trh, twh): the wakeup and reset# pins must be held high for a minimum of 5 ms. reset recovery time (trr): a minimum 1 ms reset recovery time must be allowed before astoria registers can be accessed for read or write. table 29. timing parameters for mmc/ce-ata ? all modes parameter description min max units tsdis input setup time 4 ? ns tsdih input hold time 4?ns tsdos output setup time 6 ? ns tsdoh output hold time 6 ? ns tsdckhz clock to data high z ? 18 ns tsdcklz clock to data low z 3 ? ns figure 60. reset and standby timing diagram reset# resetout wakeup firmware init complete mandatory reset pulse standby mode hard reset high-z firmware init complete mandatory reset pulse firmware init complete cy_an_mem_pmu_update.uvalid bit is set to ?1? cy_an_mem_pmu_update.uvalid bit is set to ?0? cy_an_mem_pmu_update.uvalid bit is set to ?0? tslp trpw twpw vdd (core) core power-down vddq (i/o) xtalin xtalin up & stable before wakeup asserted twh trh
cywb022xx family document number: 001-13805 rev. *m page 70 of 78 table 30. reset and standby timing parameters parameter description conditions min max units tslp sleep time ?1ms twu wakeup time from standby mode clock on xtalin 1 ? ms crystal on xtalin-xtalout 5 ? ms twh wakeup high time 5 ? ms twpw wakeup pulse width 5 ? ms trh reset# high time 5 ? ms trpw reset# pulse width clock on xtalin 1 ? ms crystal on xtalin-xtalout 5 ? ms trp reset# recovery time 1 ? ms figure 61. ac test loads and waveforms (except sd and mmc, sd and mmc are comply wi th the sd/mmc specification)
cywb022xx family document number: 001-13805 rev. *m page 71 of 78 ordering information astoria provides many options with multiple orde ring part numbers as shown in the following table: ordering code definitions ordering code package type optional features clock input frequencies (mhz) status flexboot? usb switch turbo mtp cywb0220absx2-fdxit 81- ball wlcsp (pb-free) ? 26 sample cywb0224abm-bvxies 100-ball vfbga (pb-free) 19.2, 24, 26, 48 sample cywb0224abs-bzxi 121-ball fbga (pb-free) 19.2, 24, 26, 48 production CYWB0224ABS-BVXI 100-ball vfbga (pb-free) 19.2, 24, 26, 48 production CYWB0224ABS-BVXIt 100-ball vfbga (pb- free) 19.2, 24, 26, 48 production CYWB0224ABS-BVXIes 100-ball vfbga (p b-free) 19.2, 24, 26, 48 sample cywb0224absx-fdxi 81-ball wlc sp (pb-free) 19.2, 26 sample cywb0224absx-fdxit 81-ball wlcsp (pb-free) 19.2, 26 production cywb0226abs-bvxi 100-ba ll vfbga (pb-free) ? 19.2, 24, 26, 48 production cywb0226abs-bvxit 100-ba ll vfbga (pb-free) ? 19.2, 24, 26, 48 production cywb0226absx-fdxi 81-ball wlcsp (pb-free) ? 19.2, 26 sample cywb0226absx-fdxit 81-bal l wlcsp (pb-free) ? 19.2, 26 production temperature range: i = industrial = ?40 c to +85 c x = pb-free package type: xx = bv or bb or bz or fd bv = 100-ball vfbga bz = 121-ball fbga fd = 81-ball wlcsp fixed value: x = 2 fixed value abs = gpif support base part number: xxxx = 0224 or 0226 or 0216 or 0220 marketing code: wb = west bridge astoria company id: cy = cypress xxxx abs - xi xx x x cy wb
cywb022xx family document number: 001-13805 rev. *m page 72 of 78 package diagram figure 62. 100-ball vfbga (6 6 1.0 mm) bz100 package outline, 51-85209 51-85209 *d 100-ball vfbga package outline number revision date released 51-85209 *d 02/07/2011
cywb022xx family document number: 001-13805 rev. *m page 73 of 78 figure 63. 121-ball fbga (10 10 1.20 mm) (0.30 ball diameter) package outline, 001-54471 001-54471 *c 121-ball fbga package outline number revision date released 001-54471 *c 05/30/2011
cywb022xx family document number: 001-13805 rev. *m page 74 of 78 figure 64. astoria wlcsp (3.91 3.91 0.55 mm) fn81b package outline, 001-45618 h g f e d c b a 1 2 3 4 5 6 7 8 9 j 123456789 h g f e d c b a j top view bottom view side view 001-45618 *c astoria wlcsp package outline number revision date released 001-45618 *c 02/23/2012
cywb022xx family document number: 001-13805 rev. *m page 75 of 78 acronyms document conventions units of measure acronym description cram cellular random access memory dma direct memory access ecc error correction code gpif general purpose interface mmc multimedia card mtp media transfer protocol pll phase-locked loop sd secure digital sd secure digital sdio secure digital input / output slc single-level cell spi serial peripheral interface usb universal serial bus vfbga very fine ball grid array wlcsp wafer level chip scale package symbol unit of measure c degree celsius a microampere s microsecond ma milliampere mbps mega bytes per second mhz megahertz ms millisecond ns nanosecond ? ohm pf picofarad vvolt
cywb022xx family document number: 001-13805 rev. *m page 76 of 78 document history page document title: cywb022xx family, west bridge ? : astoria? usb and mass storage peripheral controller document number: 001-13805 rev. ecn no. orig. of change submission date description of change ** 866960 vso / psz see ecn new datasheet *a 2208371 jyee / vso see ecn 1) corrected the pin name (r/b#) in table 2, updated i sb1 to i sb3 in table 3, updated table 5, updated figure 14 to figure 18 (timing diagrams), in table 6, moved ?interface bandwidth? to first row, updated table 7, updated figure 22, added figure 23 (new), updated figure 24 to 26, updated table 8, updated figure 27, added table 9 (async sram mode timing), updated figure 29 - 31, updated table 10, upda ted figure 32 - 43, updated table 11, updated table 12, updated figure 45, updated table 14, added table 16, and 21. updated figure 47. 2) added two part numbers (cywb0226abs and cywb0226abm) in the title, modified feature list (same as astoria advance information), updated features to include ?integrated usb s witch?, updated figure 1, updated usb interface (u-port), added figure 2, u pdated section 3.6, updated table 2, updated figure 14, added table 4, updated table 5-6, updated figure 15-19, updated table 7, updated figure 20-21 , updated table 8, updated figure 22-27, updated table 9, update figure 28-29, updated table 10, updated figure 30-32, updated table 11, updated figure 33-54, updated table 12, updated figure 55, updated table 13-14, updated figure 56-58, updated table 15-16, added table 17-18, updat ed table 19, updated figure 59, and added two part numbers (cywb0226 abs and cywb0226abm) in the order information (section 9). *b 2503171 vso / aesa see ecn 1. ?features? - added 3.91x3.91 mm 81-ball wlcsp to small footprint bullet. 2. ?processor interface (p-port)? - adde d ?the p-port of the wlcsp package only supports pnand and spi interface? and ?the 81-ball wlcsp package only supports interrupt.? 3. ?clocking? - added ?the 81-ball wlcsp only supports 19.2 and 26 mhz external clock input.? and tables 1 and 2 4. table 4 - added the column of ?ball #? 5. table 5 - added a new table for wlcsp pin assignment 6. figure 13 - re moved the grid line 7. figure 14 - new bal l map for wlcsp package 8. table 14 - add 33ns for trc and twc timing for wlcsp package 9. figure 55 - updated the spi timing diagram 10. ?ordering information? - added wlcsp package ordering code to the table 11. add cywb0224absx, cywb0224abmx cywb0226absx, cywb0226abmx. *c 2521024 vso / aesa see ecn 1. this version is final - removed status ?preliminary? 2. update the section of ?core power down mode? 3. note 3 of table 6 has added the requirement of ssvddq and snvddq in sd/mmc modes 4. snvddq in table 6 added note 3 5. ta b l e 1 7 , add parameter twh 6. figure 22 and figure 27 have been updated 7. ta b l e 1 8 , add parameter tavh 8. figure 28 and figure 29 have been updated 9. ta b l e 2 0 , the value of parameters ?t prog? and ?tr? have been updated 10. table 23 , removed parameter of ?ta? 11. figure 58 i2c timing diagram has been updated
cywb022xx family document number: 001-13805 rev. *m page 77 of 78 *d 2663942 vso / aesa 02/24/2009 1. feature list - add (sp and lite sp) to wlcsp 2. update the section of ?clocking? (add description of ?sp? and ?lite sp?) 3. add table 3 4. add section of ?packages and interface options? 5. add table 5 6. add ?sp? to the title of table 7 7. add table 8 (pin assignment for lite sp) 8. figure 14, change the color of avddq 9. add figure 15 for lite sp ball map 10. remove some of note [2] in table 6. 11. update the description of note [2] 12. update the table in ?order information? section. *e 2905597 vso 04/05/2010 removed part cywb 0224abm-bvxi. update d package diagrams. *f 2920278 vso / aesa 04/21/2010 added i sb1 parameter in dc specifications for all voltage supplies (except usb switch) . added contents updated links in sales, solutions, and legal information . *g 2954592 esh 06/17/10 removed inactive parts from the ordering information table *h 3057588 odc 10/13/2010 removed references to mlc nand flash. removed mlc nand parts from ordering information . added ordering code definitions . *i 3164752 anop 02/07/2011 in 'd3' row in table 8, added ?#? to dack in the 'sram interface', 'adm' and 'pnand' columns. in 'd4' row in table 8, added ?#? to drq in the 'sram interface', 'adm' and 'pnand' columns. *j 3191625 anop 03/09/2011 added table 18 (page-read command sequence for large-block devices) and figure 40 (lbd mode address cycles) added table 19 (page-read command sequence for small-block devices) and figure 42 (sbd mode address cycles) updated package diagram . *k 3465771 sirk 12/22/2011 changed stat us from confidential to final. updated mass storage support (s-port) . updated pin assignments . updated package diagram . *l 3539318 sirk 03/01/2012 updated package diagram (001-45618 from rev *b to *c). moving document to external web. *m 3665980 aasi 07/06/ 2012 updated features (removed 100-ball bga package related information). updated ordering information (updated part numbers). updated package diagram (removed 100-ball bga package related information (spec 51-85107)). document history page (continued) document title: cywb022xx family, west bridge ? : astoria? usb and mass storage peripheral controller document number: 001-13805 rev. ecn no. orig. of change submission date description of change
document number: 001-13805 rev. *m revised july 6, 2012 page 78 of 78 west bridge, astoria, antioch, and slim are trademarks of cypress semiconductor. all products and company names mentioned in th is document may be the trademarks of their respective holders. cywb022xx family ? cypress semiconductor corporation, 2007-2012. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5

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